SU1231583A1 - Pulse sequence generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency measurement and conversion equipment. The aim of the invention is to expand the functionality of the device. In the pulse train, hw co 00 00

Description

containing a master oscillator of I pulses, a pulse counter 2, trigger 6, inverter 7, register 5, a block of 3 elements AND-OR, a flash drive of microprograms A, an element AND NOT 14, an address coder 9, a delay element 8, which allowed simultaneous formation of several sequences. The invention relates to a pulse technique and can be used in frequency measurement and conversion equipment.

The aim of the invention is to expand the functionality by providing simultaneous molding of several sequences and buttons varying in several parameters (duty cycle, frequency, phase), providing an operational microprogram rebuilding.

The drawing shows a functional diagram of the pulse train generator.

The pulse sequence generator contains a master pulse generator 1, a pulse counter 2, a block of 3 elements I-ShB-, a Hbtti operative drive shkprogramgram A, register 5, trigger 6, inverter 7, Delay element 8, address encoder 9, bus 10 Start, bus P. data, spike 12 control, output bus 13, element AND NOT 14, bus 15 addresses

The output of the master oscillator 1 pulses is connected to the counting input of counter 2, to the control input of the block 3 of the AND-OR elements, and through inverter 7 to the reset input of the trigger 6 and to the input of the delay element 8, the output of which is connected to the synchronous input of the trigger 6 and the first input element AND-NOT 14, the second input element AND-NOT 14 is connected to one of the outputs of register 5 and to the control input of the address encoder 9, whose information input is connected to the control bus 12, the output of the address encoder 9 is connected to the information input of counter 2 , vytelnost and pulses, varied on several parameters em1z1H (duty cycle frequency., Laz) and providing operational firmware adjustment to achieve this goal. The pulse train generator also contains W1-W1 10 Start, 1 data, 12 controls, output 13, 15 addresses. 1 il.

the stroke of which is connected to the first information input of the 3-I-11PI block, the second information input of the AND-OR block is connected to the address bus 15, the information input of the trigger 6 is connected to the Start 10 bus, and the direct and inverse outputs of the trigger 6 are connected respectively to the second the control input of the block 3 of the AND-OR elements and the control input of the operative accumulator of the microprogram 4, whose information input is connected to the data bus 11, the output of the operative accumulator of the microprogram 4, is connected to the information input of the register 5.

The pulse train generator works in the following way. Impulse generator 1

forms a meaudpravuyu (rectangular with a duty cycle of two) pulse sequence (fon) which is fed to the counting input of counter 2. Counter 2, previously (before

 work) reset to zero, odds) O1, a sequence of parallel address codes from zero to a predetermined value. The subsequent, initial and final, values of the address codes generated by the counter 2 are determined by the state of the control bus 12 and the microprogram stored in the RAM of the microprograms 4.

A parallel code with a bit equal to AHB is fed through a block of 3 AND-OR elements to the address of the entrance of the micro-prog ramus Mivi 4.

The moment of passage of the group of BHA bits through the block of 3 elements

W1I is gated with a positive pulse half-wave of the master oscillator 1.

Trigger 6, pz of the condition of the initial installation, reset to O by the negative half-period of the frequency set by generator 1, has a high potential at output Q, which determines the mode of reading information from the cell of operative storage 4 at a given address.

Firmware drive 4 is an operational or semi-operative storage matrix,. information in which is divided into addresses, compiled informational, a word rigidly associated with its address in which it is recorded.

When an address code is sent to the address input of the microprogram A accumulator in the read mode, the information word corresponding to this address is generated at the information output of the microprogram 4 accumulator and is fed to the register 5 input.

On the falling edge of the pulses of the master oscillator 1, acting on the synchronous inputs of the register 5, information from the operative accumulator 4 is bitwise fixed to the register 5, where it is held until the next trailing edge of the positive pulse of the master oscillator 1 arrives, i.e. during the whole period of the reference frequency f.

A prerequisite for surely recording information from the firmware accumulator 4 to the register 5 at the address generated on the counter 2 is the ratio

.San.,

where the transfer time in the counter ij is the delay time on block 3

elements AND-OR; ij is the sampling time of information and the operative accumulator of firmware 4; f is the delay time

imb

re 7; ijnn - information recording time in

register 5.

Information removed (readable) from register 5 should be considered bitwise, i.e. every time

$

 five

20

30 5

0

five

0

five

583

A row of register 5 represents the output of a channel that generates the corresponding frequency of a pulsed pulse. These frequencies can be linked in phase or in other Beechodetermined parameters.

One of the bits of register 5 is assigned to control the cyclical operation of the generator, in this bit a microcommand is formed that controls the operation of the address encoder 9 and writes the initial code A into counter 2.

Operational transfer of the firmware into the operative drive 4 can be performed without breaking the non-generating sequences.

Information is recorded in the RAM 4 by the address given on the address bus 15, where the address code is fed, and on the data bus 11. - value (code) of the input information word, then via bus 10 The start occurs with a shift relative to the leading edges of the address signals and data signals a clock signal that allows the D-input to operate trigger 6. On the leading edge of the pause f, (the inverse of the signal from pulse generator I, behind the delayed delay element 8) the trigger b is set to one state and opens the block 3 of the I-IIP elements with a signal from its single output, skips to the target input of the micro drive 4 programs Partial address code supplied. n 1 bus 15 address. At the same time, the zero shoulder of trigger 6 ensures that the mode is written to the operative drive of microprogram 4, and information from the bus 11 dan-iffitx in this mode is entered into the corresponding cell of the operative drive 4. Start 10 must be cleared.

Thus, information is recorded in the operative drive 4 at the time of a pause in the period of frequency f (received from the master pulse generator J), and writing to the register 5 from the operative drive 4 occurs during the pulse in the period of frequency f, i.e. . these two processes in the operative drive come with separation in time.

The information in the operative drive A may be recorded in those cells which are not used in the formation of the pulse sequence generated at the moment of writing to the drive, i.e. The working area information of the accumulator is not distorted, but is used for the formation of working frequencies during the time divided with its entry into the accumulator. Consequently, the generation of the output frequencies of the generator is not violated when information is written to the RAM 4. Then, after preparing one of the peajnisyeMyio nodes, the address zones subroutine, it can be put into operation by supplying its address number

Maxnialp frequency should be

2 v

G7 /, IV. l., l.

2 (1 + (. -B,:, s)

1C. B

Riode onorpoy hour you set the generator 1

- polunoriod onorpoi often pulses; - end-to-end transfer time

counter 2; time delays elements I-1SHI;

- time zaderlski on block 3

thirty

 sampling time 1P1 forma 35 from RAM 4;

L ;, - write time 1И1formatsion pa register 5.

In this case, the condition must be met.

S 4 -3 S 4 -S.

i t

 g g

 V%

de i-, C, respectively, the duration of the pulse and the duration of the pause of the master oscillator 1; t, - time to turn on trigger- 50

ra 6;

, tg is the duration of the signal delay in the element of delay 3;

VSH-MSH Order 2659/56. Tirsik 81b Subscription Prod1 - 1o; shr. pr-tie, Uzhgorod, st. Project, 4

jo d 20

2S

thirty

35

YU

five

50

I-7 is the time of recording information in the operating space of the 1st to the 1st packager i. O zmu Ja and 3 obrete n and the generator of the posledonatel-nosti of impulses, a problem, a generator of impulses, a register, a counter of impulses, a trigger, an inverter, about t and l and w with and so that, in order to expand the n-1 functional capabilities, it additionally includes the element AND-NOT, the address encoder, the block of the AND-OR elements, the operative drive of the microprograms, the delay element, and the output of the master pulse generator. the counting input of the pulse counter, to the control input of the I-GSHI unit, the input of the inverter, the output of which is connected to the trigger reset input, to the delay delay input and to the buffer register register, the output of the delay element is connected to the trigger synchronization input and the first input of the N – NO element, the second input of which is connected to the synchronous input address encoder and to the output output buffer register, and the output The I-11E unit is connected to the sync-D01-1 pulse counter, the output of which is connected to the nep-jOMy information input of the block of elements AND-OR, and the format input of the address coder and the key switch to the control bus, the output of the address coder is connected to (the normal input of the pulse counter, the input lanna is connected to the input and the trigger input, are the direct and inverse outputs to which are connected respectively to the second control input of the I-GSH element block and to the control in: the microprogram memory drive, the information input which is connected to the data cable, .a address input is connected to the output of the I-ILL unit block, the second format, and the 1st input of which is connected to the bus bus, the output of the firmware driver is connected to the information input buffer The first register, the outputs of which are the outputs of the device.

Claims (1)

Forumula and I · A pulse sequence generator containing a master pulse generator, a register, a counter of 10 pulses, a trigger, an inverter, and so on, in order to expand the functionality, an additional AND-NOT address element is added to it encoder, _May 1st block of the AND-OR, operative drive firmware, the delay element, the output of the driving pulse generator is connected to the counting input of pulse counter 20 to the control input of the block elements AND-OR input of the inverter, the output of which is connected to a reset input of the trigger, to the input of the delay element and to the sync input of the buffer register 25 .ra, the output of the delay element is connected to the sync input of the trigger and the first input of the NAND element, the second input of which is connected to the sync input of the address encoder and with the control output 30 of the buffer register, and the output of the And element NOT connected to the counter clock input of the pulse generator whose output is connected to the first information input of the AND-OR element block, 35 the information input of the address encoder is connected to the control bus, the output of the address encoder is connected to the information the input of the pulse counter, the input bus is connected to the 40 information input of the trigger, the direct and inverse outputs of which are connected respectively to the second control input of the block of AND-OR elements and the control input of the operational microprogram storage device, the information input of which is connected to the data bus. the input is connected to the output of the block of AND-OR elements, the second information input 50 of which is connected to the data bus, the output of the online firmware is connected to the information input of the buffer register, the outputs of which are the outputs of the device. VINYL Order 2659/56 Circulation'816 Subscription Production polygon. ave, city of Uzhhorod, st. Project, 4