SU1704146A1 - Frame sync word separator - Google Patents

Abstract

The invention relates to automation and can be used in discrete message transmission systems for synchronizing the reception of a continuous digital stream divided into information frames. A distinctive feature of the device is. that it allows to reduce the time of entry into synchronization by alternately using the constant memory to search for the frame sync word, while the device is able to detect frame sync at any position in the frame (at the beginning and end of the frame, in any one parts of the frame, evenly distributed), and in the process of detection the probability of missing a frame sync is eliminated. The aim of the invention is to reduce the time taken to synchronize. The goal is achieved through the introduction of control block 1, code converter 2, address formers 3 and counter 5, memory blocks 4, 6, comparison block 12, divider 9. of the 11 sync word generator. 6 Il.

Description

The invention relates to automation and can be used in digital information transmission systems for synchronizing the reception of a continuous digital stream divided into information frames.

The purpose of the invention is to reduce the time of entry into synchronism.

FIG. 1 shows a block diagram of the device; in fig. 2 - electric circuit of the address driver; in fig. 3 is a frequency divider circuit; in fig. 4 is a comparison block diagram; in fig. 5 is a control block diagram; in fig. 6 shows the timing diagram of the device.

The device comprises a control unit 1, a code converter 2, an address driver 3, a main memory unit 4.

reversible counter 5, fixed memory block 6, comparison block 7, trigger 8, frequency divider 9, frame format counter 10, frame sync generator 11, second comparison block 12, error counter 13, one-shot 14,15, group mode setting inputs 16, phasing output 17, clock inputs 18,19,20, information input 21.

Shaper 3 address (figure 2) contains a binary counter 22, one-shot 23, a resistor 24, a capacitor 25.

Divider 9 frequency (fig.Z) contains a binary counter 26, one-shot 27, the element OR-28, the resistor 29. the capacitor 30.

Comparison unit 7 (FIG. 4) contains a HE element 31. An adder 32 modulo two, a HE element 33, And 34, 35 elements.

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The control unit 1 (FIG. 5) contains the triggers 36, 37 elements And 38, 39. the one-oscillator 40, the capacitor 41, the resistor 42.

The device works as follows.

The inputs of the converter 2 receives the code of the transmission of digital information (DI) or, which is the same, the code of the loop structure. The received input information Converter 2 converts the preset code, which is fed to the inputs of the imaging unit 3 addresses and the divider 9 frequency. Shaper 3 at its outputs sequentially generates address codes, the number of which is equal to the multiplicity value of the KSS following frequency, KSS following frequency, and the frequency of occurrence of the QI symbol. In the initial state, after turning on the power supply voltage, unit 4 is zeroed out (zeroing scheme is not shown).

The operation of control unit 1 consists in the appearance of an information symbol (a digital sequence element) at the device input to generate two signals at its output, which provide control of the operation of unit 4 and counter 5 (see the timing diagrams in Fig. 6). At the same time, the first flip-flop 36 switches to a single state on the clock signal fi, and at its output a logical 1 signal appears, opening the first element 38. The clock signal travels to the element outputs, thereby forming the signal of the first setting of the address generator 3 . The clock signal f following the clock fi switches the first trigger of 36 B to the zero state, and the second trigger of 37 switches to -ioe in this way: - :, h; geme, - t I 2t- zg,. c FT o .-- g., element V, 39 opens. 7a This signal m ng EYHO.S with the second t; O.I. cot1, thus, SIP-.a - i: C. E block 4. HS signal. - ..- th go-e. - .: -c And the trigger 40 is started, which by the output signal returns the second trigger 37 B ng -.c is the main component.

The operation of the shaper 3 addresses of the zclockers is that, with the PSTNT, each subsequent clock signal - accompanying the information symbol, form the address for the block 4. 3 the binary 22 is used as the basic element of the address shaper unit, the output code of which is the address block 4. With the arrival of each clock pulse, the state of the binary counter changes and the block 4 address changes accordingly. Shaper 3 addresses generates a given number of addresses corresponding to the minimum number of information

characters located between the symbols of the KCC, i.e. At the output of counter 22, a linearly varying binary code is present. After the formation of the last address, the shaper 3 returns to the initial state and its operation cycle is repeated, i.e. It works cyclically in the KCC search process. Upon detection of the CIL, operation of the address builder 3 is stopped by the output signal of the trigger 8.

In accordance with the address NA, a binary code Nc (at the first time instant zero) appears at the output of block 4, corresponding to the number of matches between the KCC code and the DI elements. This code is a presetting code for the reversible counter 5, which generates the address codes for the unit 6 that stores the reference CSS.

The arrival of digital information at the input of the device is accompanied by clock signals TI and 12 shifted relative to Ti by half a period.

The cycle of the device in the search process KCC does not exceed the duration of the period of the clock signal. In each cycle of operation, with the arrival of the clock signal Ti, the NA changes. at the output of block 4, an Nc code appears, which, according to the signal

(Fig. 1) of the control unit 1 is rewritten to the reversible counter 5. At the output of the block b, a corresponding element of the KCC appears. In block 7 of the comparison, the element of the reference CSS and QI is compared. By

a coincidence (mismatch) signal appears at the outputs of the clock signal Ti at the outputs of the comparator unit 7, which passes to the counting input (or reset input) of the reversible counter 5 Code N e with the reversing

the counter 5 enters the data inputs of block 4 and the signal (fig. bv) of the control block 1 controls the census of trees 4, the shaper 3 addresses cyclically, the length of its cy1: - L in this case is the value of p. Ti reversible counter 5 in each cycle of the device operation generates an address (KCC element number) depending on the comparison results in the previous and current cycles. After a number of work cycles

device in the cell unit 4 with the address NAJ is the code

Ncrk-1. where k is the number of KCC elements.

If there is a match in block 7

the current cycle of the last KCC element with the QI element on the counting input of the reversible counter 5 passes the next clock pulse, which causes its overflow and leads to the appearance at its output

signal overflow logic 1. With this signal, trigger 8 is switched to one state, and divider 9 is zeroed. The overflow of the reversible counter 5 indicates that the KCC code has been detected in the DI. The device goes into maintenance mode.

In this mode, the phased divider 9 generates signals at its output with a frequency proportional to the frequency of the CIL phenomenon. The frame format counter 10 counts the frame length, and in the course of this counting, the KCC code appears at the outputs of block 11. which is element-wise compared to the KCC code entering the DI.

If the number of mismatches, counted by the error counter 13, exceeds a certain threshold value, then the output of the counter 13 is the signal that triggers the one-shot 14. The output signal of which trigger 8 switches to the zero state. The device goes into search mode KCC. If the number of mismatches does not exceed the threshold value, then at the end of the frame length counting at the output of counter 10, a signal triggers the one-shot 15. The output signal of the one-shot 15 is a frame sync signal.

The control unit 1 (FIG. 5) operates in the following manner.

Trigger 36 is switched over by clock signal fi and a logical signal G opens element AND 38 appears at its output. Clock signal f 1 passes to output of element 38, thereby forming a preset signal of the reversible counter 5. Following the clock The fi clock signal f2 switches the trigger 36 to the zero state, and the trigger 37 switches to the one state, as a result of which the AND 38 element closes and the AND 39 element opens. A clock signal, f, passes to the output of the AND 39 element, thereby forming the information recording signal in block 4. By dropping the signal (at the end of the tr cycle) at the output of the And 39 element, a one-shot 40 is triggered, which returns the trigger 37 to the initial state by the output signal. With the arrival of the next clock signal fi, the operation of the control unit 1 is repeated in the order described.

Shaper 3 addresses (figure 2) works as follows.

In each cycle of operation of the former, the initial binary combination entered at its information inputs of the preset is entered into the counter 22. Therefore, counter 22 with the arrival

A clock signal changes the binary combination at its outputs, starting from the original. The initial combination is selected so that when the required number of addresses at the overflow output of counter 22 is completed, each of the signals triggering the single vibrator 23. The output signal of the single vibrator 23 acts on the preset enable input of the counter 22, writes the initial binary combination to the counter, which remains unchanged during the entire specified mode of operation. After that, the operation of the address generator 3 is repeated cyclically in the order described above.

Divider 9 frequency (fig.Z) works as follows.

On the input phasing signal coming from the output of the reversible counter 5 to the first input of the element OR 28, a one-shot 27 is triggered. Its output signal, affecting the record enable input of the counter 26, writes the initial binary combination (the counter division ratio) to it. With the arrival of each clock pulse, binary counter 26 changes its state and, when overflowed, generates a signal at the overflow output. The period of occurrence of this signal is equal to the sum of the periods of the following information symbols between two adjacent KCC symbols. The counter overflow signal, acting through the OR element 28 on the input of the one-shot 27, triggers it. The output signal of the one-shot 27 sets the counter 26 back to its original state, after which the operation of the divider 9 is repeated cyclically in the order described above.

The device is capable of detecting KCC both in the case of its location at the beginning (end) of the frame, and in the case of condensing the KCC with information symbols of other subscribers. In the first case, the output of the address maker 3 is the unchanged code, in block 4 the information on only one address is changed. In the second case, the code at the outputs of the address generator 3 is changed; in block 4, information is accumulated on the number of matches of the reference CSS with the elements of DI in several addresses, the number of which is equal to the frequency ratio of the DCC and DI. In both cases, after the KCC is detected, a signal appears at the output of the reversible counter 5, indicating the detection of the KCC.

To reduce the time to synchronization, the block 6 contains the code of n elements of the reference CIL in the device (the CSC consists of two groups of no m and n elements of

each). Due to this, KCC omissions in the search process are eliminated, which leads to a reduction in search time. During the synchronization process, the KCC generator 11 generates the full KCC code, allowing comparison in all elements.

The block diagram of the device and the examples of block implementation show the symbols (a ... e) of the signals, the form of which is shown in FIG. 6. FIG. 6 shows time diagrams for two cases: information transfer rates at the frequencies fi and fi. Timing diagrams illustrate that device operation cycles in the element-by-element comparison process do not change when the CPU speed changes (or the frame compression structure changes).

Claims (1)

Claims An apparatus for allocating a frame sync word comprising a frame format counter, two one-vibrators, a frame sync word generator, a trigger, a first comparison unit and an error counter, the overflow output of the frame format counter being connected to the input of the first single-vibrator. the output of which is connected to the reset input of the error counter, the inverse output of the trigger is connected to the shift enable input of the frame sync word generator, the output of which is connected to the first input of the first comparator unit, the second input of which is the information input of the device, the output of the first reference unit is connected to the counter input of the counter errors, the overflow output of which is connected to the input of the second sibling vibrator, the output of which is connected to the trigger reset input, characterized in that, in order to reduce the time synchronization, a code converter, an address driver, a divider h & a control unit, a reversible counter, a random access memory unit, a second comparison unit and a fixed memory unit are inputted into it, and the group of inputs of the code converter is a group of task inputs device mode, a group of outputs of the code converter is connected to a group of information inputs of the address generator and a group of information inputs of a frequency divider, a group of outputs of the address generator is connected to a group of address inputs of the RAM block, a group of outputs of which is connected to a group of information inputs of a reversible counter, a group of the bit outputs of which are connected to the group of information inputs of the RAM block and the group of address inputs of the fixed memory block whose output is It is connected to the first information input of the second comparison unit, the second information input of which is connected to the second information input of the first comparison unit, the gate input of which is connected to The gate input of the second comparison unit, with the information input of the address driver, with the first clock input of the control unit, is the first clock input of the device, the information the input of the frequency divider is connected to the second clock input of the control unit and is the second clock input of the device, the third clock input of the control unit is the third clock input of the device, the first output of the control unit is connected to the write enable input of the memory block, the second output of the control unit is connected to counting input the input of which is connected to the equality output of the second comparator unit, the inequality output of which is connected to the reset input of the reversible counter, the output of which is connected to the recording resolution input of the frequency divider and the installation input to the trigger unit, the output of the first single-oscillator is the phase output The device is connected to the direct output of the three gers connected to the write enable input of the address mapper and to the chip select input of the permanent memory block; the counting resolution enable input of the frame format counter is connected to the inverse trigger output. Speed code qi 16 C Output output Fm.1 / 7 FIG g fig.Z FIG 4 fr F 36 S 57 Vu.n 42 0-SIR L eight 39 L. r 4 / TJ w Fi g 5  Sh.p ppppppppppppppppppppppppppp . F p p p p p p p and p and p p p p A p p p p p and and p p p p p p .-p p l p p Jl a) y | ghee and |. Y four pn I P I am P GPP P GPP P 4 p p. P / L .1 P / 2 I and) zx: and F p n p p  DC n n n n n n n P Jl I P I am and Jl one D (1 P P x: