NO870225L - Datamaskinsystem med hurtigbuffer. - Google Patents

Datamaskinsystem med hurtigbuffer.

Info

Publication number
NO870225L
NO870225L NO870225A NO870225A NO870225L NO 870225 L NO870225 L NO 870225L NO 870225 A NO870225 A NO 870225A NO 870225 A NO870225 A NO 870225A NO 870225 L NO870225 L NO 870225L
Authority
NO
Norway
Prior art keywords
tlb
type
memory
computer system
conditions
Prior art date
Application number
NO870225A
Other languages
English (en)
Norwegian (no)
Other versions
NO870225D0 (no
Inventor
Danny L Freitas
Craig C Hansen
Christopher Rowen
Original Assignee
Mips Computer Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mips Computer Systems Inc filed Critical Mips Computer Systems Inc
Publication of NO870225D0 publication Critical patent/NO870225D0/no
Publication of NO870225L publication Critical patent/NO870225L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Polarising Elements (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Telephonic Communication Services (AREA)
NO870225A 1986-05-02 1987-01-20 Datamaskinsystem med hurtigbuffer. NO870225L (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US85907586A 1986-05-02 1986-05-02

Publications (2)

Publication Number Publication Date
NO870225D0 NO870225D0 (no) 1987-01-20
NO870225L true NO870225L (no) 1987-11-03

Family

ID=25329962

Family Applications (1)

Application Number Title Priority Date Filing Date
NO870225A NO870225L (no) 1986-05-02 1987-01-20 Datamaskinsystem med hurtigbuffer.

Country Status (10)

Country Link
EP (1) EP0244532B1 (fr)
JP (1) JPH0614324B2 (fr)
KR (1) KR870011536A (fr)
AT (1) ATE99436T1 (fr)
CA (1) CA1280831C (fr)
DE (1) DE3689474T2 (fr)
DK (1) DK61187A (fr)
IE (1) IE870173L (fr)
IL (1) IL81401A (fr)
NO (1) NO870225L (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920890A (en) * 1996-11-14 1999-07-06 Motorola, Inc. Distributed tag cache memory system and method for storing data in the same
JP4576172B2 (ja) 2004-07-29 2010-11-04 富士通株式会社 演算処理装置，情報処理装置及び演算処理装置の制御方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US3800286A (en) * 1972-08-24 1974-03-26 Honeywell Inf Systems Address development technique utilizing a content addressable memory
US4357656A (en) 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
US4473878A (en) 1981-11-23 1984-09-25 Motorola, Inc. Memory management unit
US4558433A (en) * 1983-05-31 1985-12-10 International Business Machines Corporation Multi-port register implementations

Also Published As

Publication number Publication date
IE870173L (en) 1987-11-02
DE3689474T2 (de) 1994-04-28
IL81401A0 (en) 1987-08-31
DK61187D0 (da) 1987-02-06
EP0244532A3 (en) 1989-05-10
NO870225D0 (no) 1987-01-20
EP0244532A2 (fr) 1987-11-11
DK61187A (da) 1987-11-03
KR870011536A (ko) 1987-12-24
JPH0614324B2 (ja) 1994-02-23
ATE99436T1 (de) 1994-01-15
DE3689474D1 (de) 1994-02-10
EP0244532B1 (fr) 1993-12-29
JPS62260245A (ja) 1987-11-12
CA1280831C (fr) 1991-02-26
IL81401A (en) 1991-06-10

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