DK59487A - Lager for en databehandlingsenhed - Google Patents

Lager for en databehandlingsenhed

Info

Publication number
DK59487A
DK59487A DK059487A DK59487A DK59487A DK 59487 A DK59487 A DK 59487A DK 059487 A DK059487 A DK 059487A DK 59487 A DK59487 A DK 59487A DK 59487 A DK59487 A DK 59487A
Authority
DK
Denmark
Prior art keywords
cache
stores
processing unit
data processing
address
Prior art date
Application number
DK059487A
Other languages
English (en)
Other versions
DK59487D0 (da
Inventor
John P Moussouris
Lester M Crudele
Steven Przybylski
Original Assignee
Mips Computer Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mips Computer Systems Inc filed Critical Mips Computer Systems Inc
Publication of DK59487D0 publication Critical patent/DK59487D0/da
Publication of DK59487A publication Critical patent/DK59487A/da

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Debugging And Monitoring (AREA)
  • Communication Control (AREA)
DK059487A 1986-02-06 1987-02-05 Lager for en databehandlingsenhed DK59487A (da)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/827,269 US4953073A (en) 1986-02-06 1986-02-06 Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories

Publications (2)

Publication Number Publication Date
DK59487D0 DK59487D0 (da) 1987-02-05
DK59487A true DK59487A (da) 1987-08-07

Family

ID=25248766

Family Applications (1)

Application Number Title Priority Date Filing Date
DK059487A DK59487A (da) 1986-02-06 1987-02-05 Lager for en databehandlingsenhed

Country Status (13)

Country Link
US (2) US4953073A (da)
EP (1) EP0231574B1 (da)
JP (1) JPS62184551A (da)
KR (1) KR950012733B1 (da)
AT (1) ATE83567T1 (da)
CA (1) CA1273715A (da)
DE (1) DE3687307T2 (da)
DK (1) DK59487A (da)
ES (1) ES2005092A6 (da)
GR (1) GR870204B (da)
IE (1) IE870309L (da)
IL (1) IL81238A (da)
NO (1) NO870415L (da)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1575939B1 (de) * 1967-01-21 1973-01-25 Jurid Werke Gmbh Reibbelaganordnung

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953073A (en) * 1986-02-06 1990-08-28 Mips Computer Systems, Inc. Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
US5067078A (en) * 1989-04-17 1991-11-19 Motorola, Inc. Cache which provides status information
JPH0740247B2 (ja) * 1989-06-20 1995-05-01 松下電器産業株式会社 キャッシュメモリ装置
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
US5077826A (en) * 1989-08-09 1991-12-31 International Business Machines Corporation Cache performance in an information handling system employing page searching
US5297270A (en) * 1989-11-13 1994-03-22 Zenith Data Systems Corporation Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size
EP0446534A3 (en) * 1990-03-16 1992-08-05 John Fluke Mfg. Co., Inc. Method of functionally testing cache tag rams in limited-access processor systems
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
JPH05108484A (ja) * 1990-06-07 1993-04-30 Intel Corp キヤツシユメモリ
US5732241A (en) * 1990-06-27 1998-03-24 Mos Electronics, Corp. Random access cache memory controller and system
US5276833A (en) * 1990-07-02 1994-01-04 Chips And Technologies, Inc. Data cache management system with test mode using index registers and CAS disable and posted write disable
US5835945A (en) * 1990-08-06 1998-11-10 Ncr Corporation Memory system with write buffer, prefetch and internal caches
JPH04128946A (ja) * 1990-09-20 1992-04-30 Fujitsu Ltd アドレス変換方式
US6275901B1 (en) * 1990-10-09 2001-08-14 Intel Corporation Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array
US5412787A (en) * 1990-11-21 1995-05-02 Hewlett-Packard Company Two-level TLB having the second level TLB implemented in cache tag RAMs
JP2646854B2 (ja) * 1990-12-18 1997-08-27 三菱電機株式会社 マイクロプロセッサ
JP2703418B2 (ja) * 1991-04-24 1998-01-26 株式会社東芝 中央演算処理装置
EP0525308A1 (en) * 1991-07-31 1993-02-03 International Business Machines Corporation Memory map for processor cache macro
US6230233B1 (en) 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5634027A (en) * 1991-11-20 1997-05-27 Kabushiki Kaisha Toshiba Cache memory system for multiple processors with collectively arranged cache tag memories
US5469555A (en) * 1991-12-19 1995-11-21 Opti, Inc. Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US5276878A (en) * 1992-10-07 1994-01-04 International Business Machines Corporation Method and system for task memory management in a multi-tasking data processing system
US5572235A (en) * 1992-11-02 1996-11-05 The 3Do Company Method and apparatus for processing image data
US5596693A (en) * 1992-11-02 1997-01-21 The 3Do Company Method for controlling a spryte rendering processor
US5481275A (en) 1992-11-02 1996-01-02 The 3Do Company Resolution enhancement for video display using multi-line interpolation
US5838389A (en) * 1992-11-02 1998-11-17 The 3Do Company Apparatus and method for updating a CLUT during horizontal blanking
GB2273856B (en) * 1992-12-22 1996-12-18 Advanced Risc Mach Ltd Pixel display palette
US5752073A (en) * 1993-01-06 1998-05-12 Cagent Technologies, Inc. Digital signal processor architecture
GB2275119B (en) * 1993-02-03 1997-05-14 Motorola Inc A cached processor
US5574923A (en) * 1993-05-10 1996-11-12 Intel Corporation Method and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessor
EP0625746A1 (de) * 1993-05-19 1994-11-23 Siemens Nixdorf Informationssysteme Aktiengesellschaft Befehlsaufbereitungseinheit für Verarbeitungsprozessoren in Datenverarbeitungsanlagen
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US5726937A (en) * 1994-01-31 1998-03-10 Norand Corporation Flash memory system having memory cache
US5870599A (en) * 1994-03-01 1999-02-09 Intel Corporation Computer system employing streaming buffer for instruction preetching
US6129458A (en) * 1994-03-23 2000-10-10 At&T Global Information Solutions Company Cache optimization method
US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
US6687790B2 (en) * 1994-08-03 2004-02-03 Intel Corporation Single bank associative cache
US5636354A (en) * 1994-09-06 1997-06-03 Motorola Inc. Data processor with serially accessed set associative memory cache interface and method
EP1278125A2 (en) 1994-10-14 2003-01-22 MIPS Technologies, Inc. Indexing and multiplexing of interleaved cache memory arrays
WO1996012231A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
TW358907B (en) * 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
US6128700A (en) 1995-05-17 2000-10-03 Monolithic System Technology, Inc. System utilizing a DRAM array as a next level cache memory and method for operating same
US7483935B2 (en) * 1995-08-16 2009-01-27 Microunity Systems Engineering, Inc. System and method to implement a matrix multiply unit of a broadband processor
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US7301541B2 (en) * 1995-08-16 2007-11-27 Microunity Systems Engineering, Inc. Programmable processor and method with wide operations
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US6065108A (en) * 1996-01-24 2000-05-16 Sun Microsystems Inc Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same
US5960453A (en) 1996-06-13 1999-09-28 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
US6819325B2 (en) 2000-03-07 2004-11-16 Microsoft Corporation API communications for vertex and pixel shaders
US7159041B2 (en) * 2000-03-07 2007-01-02 Microsoft Corporation Method and system for defining and controlling algorithmic elements in a graphics display system
JP5076133B2 (ja) * 2000-06-27 2012-11-21 インベンサス、コーポレーション フラッシュを備えた集積回路
FR2818145B1 (fr) * 2000-12-18 2003-11-28 Oreal Compositions cosmetiques antisolaires a base d'un melange synergetique de filtres et utilisations
US7023431B2 (en) * 2001-03-01 2006-04-04 Microsoft Corporation Method and system for providing data to a graphics chip in a graphics display system
US6828975B2 (en) * 2001-03-01 2004-12-07 Microsoft Corporation Method and system for managing graphics objects in a graphics display system
US6831635B2 (en) * 2001-03-01 2004-12-14 Microsoft Corporation Method and system for providing a unified API for both 2D and 3D graphics objects
US6874150B2 (en) * 2001-03-01 2005-03-29 Microsoft Corporation Method and system for maintaining connections between surfaces and objects in a graphics display system
US6812923B2 (en) 2001-03-01 2004-11-02 Microsoft Corporation Method and system for efficiently transferring data objects within a graphics display system
US7310706B1 (en) * 2001-06-01 2007-12-18 Mips Technologies, Inc. Random cache line refill
US7024414B2 (en) * 2001-08-06 2006-04-04 Sensage, Inc. Storage of row-column data
WO2003021423A2 (en) * 2001-09-04 2003-03-13 Microunity Systems Engineering, Inc. System and method for performing multiplication
EP1556868B1 (en) * 2002-10-28 2007-09-05 SanDisk Corporation Automated wear leveling in non-volatile storage systems
US20050182903A1 (en) * 2004-02-12 2005-08-18 Mips Technologies, Inc. Apparatus and method for preventing duplicate matching entries in a translation lookaside buffer
US7558939B2 (en) * 2005-03-08 2009-07-07 Mips Technologies, Inc. Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
DE602005023273D1 (de) * 2005-04-29 2010-10-14 St Microelectronics Srl Ein verbessertes Cache-Speicher System
CN103399827B (zh) 2013-07-25 2015-11-25 华为技术有限公司 存储装置、执行访问操作的系统和方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4084230A (en) * 1976-11-29 1978-04-11 International Business Machines Corporation Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
US4532587A (en) * 1981-08-26 1985-07-30 Texas Instruments Incorporated Single chip processor connected to an external memory chip
EP0080844A1 (en) * 1981-11-25 1983-06-08 The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and The preparation of adducts which may be used in the preparation of compound semiconductor materials
CH652912A5 (de) * 1982-02-23 1985-12-13 Sulzer Ag Den schaft einer in einen roehrenknochen einsetzbaren endoprothese zentrierende halterung.
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
US4527232A (en) * 1982-07-02 1985-07-02 Sun Microsystems, Inc. High-speed memory and memory management system
JPS60122443A (ja) * 1983-12-05 1985-06-29 Mitsubishi Electric Corp 情報処理装置
US4587610A (en) * 1984-02-10 1986-05-06 Prime Computer, Inc. Address translation systems for high speed computer memories
US4646233A (en) * 1984-06-20 1987-02-24 Weatherford James R Physical cache unit for computer
US4794524A (en) * 1984-07-03 1988-12-27 Zilog, Inc. Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
JP2539357B2 (ja) * 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
US4821171A (en) * 1985-05-07 1989-04-11 Prime Computer, Inc. System of selective purging of address translation in computer memories
US4785398A (en) * 1985-12-19 1988-11-15 Honeywell Bull Inc. Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
US4953073A (en) * 1986-02-06 1990-08-28 Mips Computer Systems, Inc. Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US4811209A (en) * 1986-07-31 1989-03-07 Hewlett-Packard Company Cache memory with multiple valid bits for each data indication the validity within different contents
US4882673A (en) * 1987-10-02 1989-11-21 Advanced Micro Devices, Inc. Method and apparatus for testing an integrated circuit including a microprocessor and an instruction cache

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1575939B1 (de) * 1967-01-21 1973-01-25 Jurid Werke Gmbh Reibbelaganordnung

Also Published As

Publication number Publication date
DE3687307T2 (de) 1993-04-15
CA1273715A (en) 1990-09-04
KR870008253A (ko) 1987-09-25
DK59487D0 (da) 1987-02-05
IL81238A0 (en) 1987-08-31
NO870415L (no) 1987-08-07
EP0231574B1 (en) 1992-12-16
EP0231574A2 (en) 1987-08-12
DE3687307D1 (de) 1993-01-28
ATE83567T1 (de) 1993-01-15
GR870204B (en) 1987-06-09
KR950012733B1 (ko) 1995-10-20
JPS62184551A (ja) 1987-08-12
US4953073A (en) 1990-08-28
ES2005092A6 (es) 1989-03-01
US5113506A (en) 1992-05-12
NO870415D0 (no) 1987-02-03
IL81238A (en) 1990-09-17
IE870309L (en) 1987-08-06
EP0231574A3 (en) 1989-06-07

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Legal Events

Date Code Title Description
AHB Application shelved due to non-payment