NO20051939L - Arkitektur for hoyhastighets programmerbar logisk anordning (PLD) uten bruk av DC-effekt. - Google Patents
Arkitektur for hoyhastighets programmerbar logisk anordning (PLD) uten bruk av DC-effekt.Info
- Publication number
- NO20051939L NO20051939L NO20051939A NO20051939A NO20051939L NO 20051939 L NO20051939 L NO 20051939L NO 20051939 A NO20051939 A NO 20051939A NO 20051939 A NO20051939 A NO 20051939A NO 20051939 L NO20051939 L NO 20051939L
- Authority
- NO
- Norway
- Prior art keywords
- pld
- logic
- bit
- logic device
- architecture
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17784—Structural details for adapting physical parameters for supply voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/251,402 US6809550B2 (en) | 2002-09-20 | 2002-09-20 | High speed zero DC power programmable logic device (PLD) architecture |
PCT/US2003/024983 WO2004027545A2 (en) | 2002-09-20 | 2003-08-06 | High speed zero dc power programmable logic device (pld) architecture |
Publications (2)
Publication Number | Publication Date |
---|---|
NO20051939D0 NO20051939D0 (no) | 2005-04-20 |
NO20051939L true NO20051939L (no) | 2005-06-20 |
Family
ID=31992730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO20051939A NO20051939L (no) | 2002-09-20 | 2005-04-20 | Arkitektur for hoyhastighets programmerbar logisk anordning (PLD) uten bruk av DC-effekt. |
Country Status (10)
Country | Link |
---|---|
US (1) | US6809550B2 (zh) |
EP (1) | EP1547248A4 (zh) |
JP (1) | JP2006500819A (zh) |
KR (1) | KR20050049499A (zh) |
CN (1) | CN100369381C (zh) |
AU (1) | AU2003264029A1 (zh) |
CA (1) | CA2499277A1 (zh) |
NO (1) | NO20051939L (zh) |
TW (1) | TWI286681B (zh) |
WO (1) | WO2004027545A2 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7400167B2 (en) * | 2005-08-16 | 2008-07-15 | Altera Corporation | Apparatus and methods for optimizing the performance of programmable logic devices |
US7129745B2 (en) * | 2004-05-19 | 2006-10-31 | Altera Corporation | Apparatus and methods for adjusting performance of integrated circuits |
US20060119382A1 (en) * | 2004-12-07 | 2006-06-08 | Shumarayev Sergey Y | Apparatus and methods for adjusting performance characteristics of programmable logic devices |
US7437584B2 (en) * | 2006-02-27 | 2008-10-14 | Atmel Corporation | Apparatus and method for reducing power consumption in electronic devices |
TWI661676B (zh) * | 2018-08-01 | 2019-06-01 | 新唐科技股份有限公司 | 可程式陣列邏輯 |
CN116593748B (zh) * | 2023-05-23 | 2023-11-28 | 深圳市费思泰克科技有限公司 | 用于新能源太阳能逆变器测试的大功率可编程直流电源 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4124899A (en) | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
US4879688A (en) * | 1985-03-04 | 1989-11-07 | Lattice Semiconductor Corporation | In-system programmable logic device |
US4684830A (en) | 1985-03-22 | 1987-08-04 | Monolithic Memories, Inc. | Output circuit for a programmable logic array |
US4703206A (en) * | 1985-11-19 | 1987-10-27 | Signetics Corporation | Field-programmable logic device with programmable foldback to control number of logic levels |
US4789951A (en) * | 1986-05-16 | 1988-12-06 | Advanced Micro Devices, Inc. | Programmable array logic cell |
US4922411A (en) | 1988-12-27 | 1990-05-01 | Atmel Corporation | Memory cell circuit with supplemental current |
US4959564A (en) * | 1989-01-06 | 1990-09-25 | Sgs-Thomson Microelectronics, Inc. | Sense amplifier power down circuitry for programmable logic device |
US5272674A (en) | 1992-09-21 | 1993-12-21 | Atmel Corporation | High speed memory sense amplifier with noise reduction |
US5315177A (en) | 1993-03-12 | 1994-05-24 | Micron Semiconductor, Inc. | One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture |
US5410268A (en) | 1993-09-08 | 1995-04-25 | Advanced Micro Devices, Inc. | Latching zero-power sense amplifier with cascode |
US5440508A (en) | 1994-02-09 | 1995-08-08 | Atmel Corporation | Zero power high speed programmable circuit device architecture |
US5532623A (en) | 1994-10-21 | 1996-07-02 | Waferscale Integration, Inc. | Sense amplifier with read current tracking and zero standby power consumption |
US5568066A (en) | 1994-11-17 | 1996-10-22 | Advanced Micro Devices, Inc. | Sense amplifier and or gate for a high density programmable logic device |
US5565793A (en) * | 1995-08-22 | 1996-10-15 | Altera Corporation | Programmable logic array integrated circuit devices with regions of enhanced interconnectivity |
US5734275A (en) | 1996-07-18 | 1998-03-31 | Advanced Micro Devices, Inc. | Programmable logic device having a sense amplifier with virtual ground |
US5909125A (en) * | 1996-12-24 | 1999-06-01 | Xilinx, Inc. | FPGA using RAM control signal lines as routing or logic resources after configuration |
US5974242A (en) | 1997-09-25 | 1999-10-26 | The United States Of America As Represented By The Secretary Of The Army | Methods and computer programs for minimizing logic circuit design using identity cells |
US5963496A (en) | 1998-04-22 | 1999-10-05 | Atmel Corporation | Sense amplifier with zero power idle mode |
US6236230B1 (en) | 1998-07-21 | 2001-05-22 | Cypress Semiconductor Corp. | Method, architecture and circuit for product term allocation |
US6038194A (en) * | 1998-12-28 | 2000-03-14 | Philips Electronics North America Corporation | Memory decoder with zero static power |
US6157211A (en) * | 1999-04-14 | 2000-12-05 | Xilinx, Inc. | FPGA using RAM control signal lines as routing or logic resources after configuration |
US6353331B1 (en) * | 2000-07-10 | 2002-03-05 | Xilinx, Inc. | Complex programmable logic device with lookup table |
-
2002
- 2002-09-20 US US10/251,402 patent/US6809550B2/en not_active Expired - Fee Related
-
2003
- 2003-08-06 AU AU2003264029A patent/AU2003264029A1/en not_active Abandoned
- 2003-08-06 JP JP2004537648A patent/JP2006500819A/ja not_active Withdrawn
- 2003-08-06 KR KR1020057004863A patent/KR20050049499A/ko not_active Application Discontinuation
- 2003-08-06 WO PCT/US2003/024983 patent/WO2004027545A2/en active Application Filing
- 2003-08-06 CN CNB038251981A patent/CN100369381C/zh not_active Expired - Fee Related
- 2003-08-06 CA CA002499277A patent/CA2499277A1/en not_active Abandoned
- 2003-08-06 EP EP03797833A patent/EP1547248A4/en not_active Withdrawn
- 2003-09-03 TW TW092124311A patent/TWI286681B/zh not_active IP Right Cessation
-
2005
- 2005-04-20 NO NO20051939A patent/NO20051939L/no not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
AU2003264029A1 (en) | 2004-04-08 |
JP2006500819A (ja) | 2006-01-05 |
TW200417829A (en) | 2004-09-16 |
KR20050049499A (ko) | 2005-05-25 |
WO2004027545A2 (en) | 2004-04-01 |
TWI286681B (en) | 2007-09-11 |
CN100369381C (zh) | 2008-02-13 |
CA2499277A1 (en) | 2004-04-01 |
WO2004027545B1 (en) | 2004-08-19 |
US6809550B2 (en) | 2004-10-26 |
EP1547248A2 (en) | 2005-06-29 |
EP1547248A4 (en) | 2006-08-23 |
US20040056679A1 (en) | 2004-03-25 |
CN1695304A (zh) | 2005-11-09 |
WO2004027545A3 (en) | 2004-06-24 |
NO20051939D0 (no) | 2005-04-20 |
AU2003264029A8 (en) | 2004-04-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FC2A | Withdrawal, rejection or dismissal of laid open patent application |