NL143070B - Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze. - Google Patents

Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze.

Info

Publication number
NL143070B
NL143070B NL646404321A NL6404321A NL143070B NL 143070 B NL143070 B NL 143070B NL 646404321 A NL646404321 A NL 646404321A NL 6404321 A NL6404321 A NL 6404321A NL 143070 B NL143070 B NL 143070B
Authority
NL
Netherlands
Prior art keywords
manufactured
substrate
application
metal parts
intermediate space
Prior art date
Application number
NL646404321A
Other languages
English (en)
Dutch (nl)
Other versions
NL6404321A (de
Inventor
Reinier De Werdt
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Priority to NL646404321A priority Critical patent/NL143070B/xx
Priority to DK196265AA priority patent/DK119782B/da
Priority to SE5001/65A priority patent/SE323261B/xx
Priority to GB16247/65A priority patent/GB1081472A/en
Priority to DE1521414A priority patent/DE1521414C3/de
Priority to US448741A priority patent/US3490943A/en
Priority to CH541165A priority patent/CH450863A/de
Priority to AT361965A priority patent/AT259015B/de
Priority to BE662830A priority patent/BE662830A/xx
Priority to FR14045A priority patent/FR1437781A/fr
Publication of NL6404321A publication Critical patent/NL6404321A/xx
Publication of NL143070B publication Critical patent/NL143070B/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04Coating on selected surface areas, e.g. using masks
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04Coating on selected surface areas, e.g. using masks
    • C23C14/042Coating on selected surface areas, e.g. using masks using masks
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • HELECTRICITY
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85203Thermocompression bonding
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/944Shadow
NL646404321A 1964-04-21 1964-04-21 Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze. NL143070B (nl)

Priority Applications (10)

Application Number Priority Date Filing Date Title
NL646404321A NL143070B (nl) 1964-04-21 1964-04-21 Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze.
DK196265AA DK119782B (da) 1964-04-21 1965-04-14 Fremgangsmåde til dannelse af metallag, der ligger ved siden af hinanden og er adskilt af en snæver spalte, på et underlag.
SE5001/65A SE323261B (de) 1964-04-21 1965-04-14
GB16247/65A GB1081472A (en) 1964-04-21 1965-04-15 Improvements in or relating to methods of providing separated metal layers side by side on a support
DE1521414A DE1521414C3 (de) 1964-04-21 1965-04-15 Verfahren zum Aufbringen von nebeneinander liegenden, durch einen engen Zwischenraum voneinander getrennten Metallschichten auf eine Unterlage
US448741A US3490943A (en) 1964-04-21 1965-04-16 Method of forming juxtaposed metal layers separated by a narrow gap on a substrate and objects manufactured by the use of such methods
CH541165A CH450863A (de) 1964-04-21 1965-04-20 Verfahren zum Aufbringen von nebeneinander liegenden, durch einen Zwischenraum voneinander getrennten Metallschichten auf eine Unterlage und nach diesem Verfahren auf einer Unterlage hergestellte Metallschichten
AT361965A AT259015B (de) 1964-04-21 1965-04-20 Verfahren zum Aufbringen von nebeneinander liegenden, durch einen engen Zwischenraum voneinander getrennten Metallschichten auf eine Unterlage
BE662830A BE662830A (de) 1964-04-21 1965-04-21
FR14045A FR1437781A (fr) 1964-04-21 1965-04-21 Procédé pour appliquer sur un support des couches métalliques séparées par un interstice

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL646404321A NL143070B (nl) 1964-04-21 1964-04-21 Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze.

Publications (2)

Publication Number Publication Date
NL6404321A NL6404321A (de) 1965-10-22
NL143070B true NL143070B (nl) 1974-08-15

Family

ID=19789874

Family Applications (1)

Application Number Title Priority Date Filing Date
NL646404321A NL143070B (nl) 1964-04-21 1964-04-21 Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze.

Country Status (9)

Country Link
US (1) US3490943A (de)
AT (1) AT259015B (de)
BE (1) BE662830A (de)
CH (1) CH450863A (de)
DE (1) DE1521414C3 (de)
DK (1) DK119782B (de)
GB (1) GB1081472A (de)
NL (1) NL143070B (de)
SE (1) SE323261B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH476398A (de) * 1968-03-01 1969-07-31 Ibm Verfahren zur Herstellung feiner geätzter Muster
US3977071A (en) * 1969-09-29 1976-08-31 Texas Instruments Incorporated High depth-to-width ratio etching process for monocrystalline germanium semiconductor materials
DE2120388A1 (de) * 1970-04-28 1971-12-16 Agency Ind Science Techn Verbindungshalbleitervorrichtung
US3920861A (en) * 1972-12-18 1975-11-18 Rca Corp Method of making a semiconductor device
US4111725A (en) * 1977-05-06 1978-09-05 Bell Telephone Laboratories, Incorporated Selective lift-off technique for fabricating gaas fets
DE2754066A1 (de) * 1977-12-05 1979-06-13 Siemens Ag Herstellung einer integrierten schaltung mit abgestuften schichten aus isolations- und elektrodenmaterial
DE3028718C2 (de) * 1979-07-31 1982-08-19 Sharp K.K., Osaka Dünnfilmtransistor in Verbindung mit einer Anzeigevorrichtung
JPS60103676A (ja) * 1983-11-11 1985-06-07 Seiko Instr & Electronics Ltd 薄膜トランジスタアレイの製造方法
US5017459A (en) * 1989-04-26 1991-05-21 Eastman Kodak Company Lift-off process
US5672282A (en) * 1996-01-25 1997-09-30 The Whitaker Corporation Process to preserve silver metal while forming integrated circuits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB967002A (en) * 1961-05-05 1964-08-19 Standard Telephones Cables Ltd Improvements in or relating to semiconductor devices
US3303071A (en) * 1964-10-27 1967-02-07 Bell Telephone Labor Inc Fabrication of a semiconductive device with closely spaced electrodes

Also Published As

Publication number Publication date
GB1081472A (en) 1967-08-31
DE1521414C3 (de) 1975-08-14
US3490943A (en) 1970-01-20
NL6404321A (de) 1965-10-22
DE1521414B2 (de) 1975-01-09
AT259015B (de) 1967-12-27
SE323261B (de) 1970-04-27
DK119782B (da) 1971-02-22
CH450863A (de) 1968-04-30
BE662830A (de) 1965-10-21
DE1521414A1 (de) 1969-10-09

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