CH476398A - Verfahren zur Herstellung feiner geätzter Muster - Google Patents

Verfahren zur Herstellung feiner geätzter Muster

Info

Publication number
CH476398A
CH476398A CH313068A CH313068A CH476398A CH 476398 A CH476398 A CH 476398A CH 313068 A CH313068 A CH 313068A CH 313068 A CH313068 A CH 313068A CH 476398 A CH476398 A CH 476398A
Authority
CH
Switzerland
Prior art keywords
producing fine
etched patterns
fine etched
patterns
producing
Prior art date
Application number
CH313068A
Other languages
English (en)
Inventor
Forster Theodor
Mohr Theodor
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to CH313068A priority Critical patent/CH476398A/de
Priority to FR1600776D priority patent/FR1600776A/fr
Priority to DE1908901A priority patent/DE1908901C3/de
Priority to GB00804/69A priority patent/GB1255039A/en
Publication of CH476398A publication Critical patent/CH476398A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
CH313068A 1968-03-01 1968-03-01 Verfahren zur Herstellung feiner geätzter Muster CH476398A (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CH313068A CH476398A (de) 1968-03-01 1968-03-01 Verfahren zur Herstellung feiner geätzter Muster
FR1600776D FR1600776A (de) 1968-03-01 1968-12-30
DE1908901A DE1908901C3 (de) 1968-03-01 1969-02-22 Verfahren zum Herstellen von Halbleiterbauelementen kleiner Abmessungen
GB00804/69A GB1255039A (en) 1968-03-01 1969-02-28 Improvements relating to the manufacture of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH313068A CH476398A (de) 1968-03-01 1968-03-01 Verfahren zur Herstellung feiner geätzter Muster

Publications (1)

Publication Number Publication Date
CH476398A true CH476398A (de) 1969-07-31

Family

ID=4249256

Family Applications (1)

Application Number Title Priority Date Filing Date
CH313068A CH476398A (de) 1968-03-01 1968-03-01 Verfahren zur Herstellung feiner geätzter Muster

Country Status (4)

Country Link
CH (1) CH476398A (de)
DE (1) DE1908901C3 (de)
FR (1) FR1600776A (de)
GB (1) GB1255039A (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5157167A (de) * 1974-09-19 1976-05-19 Philips Nv
DE2134528B2 (de) * 1970-09-02 1979-04-19 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Feldeffekt-Transistor, Verfahren zu dessen Herstellung und Verwendung des Feldeffekt-Transistors in einer integrierten Schaltung

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2824026A1 (de) * 1978-06-01 1979-12-20 Licentia Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
GB2127751B (en) * 1982-10-06 1986-04-23 Plessey Co Plc Producing narrow features in electrical devices
DE3915650A1 (de) * 1989-05-12 1990-11-15 Siemens Ag Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL143070B (nl) * 1964-04-21 1974-08-15 Philips Nv Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2134528B2 (de) * 1970-09-02 1979-04-19 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Feldeffekt-Transistor, Verfahren zu dessen Herstellung und Verwendung des Feldeffekt-Transistors in einer integrierten Schaltung
JPS5157167A (de) * 1974-09-19 1976-05-19 Philips Nv

Also Published As

Publication number Publication date
DE1908901B2 (de) 1976-12-09
FR1600776A (de) 1970-07-27
DE1908901A1 (de) 1969-09-25
GB1255039A (en) 1971-11-24
DE1908901C3 (de) 1981-09-24

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Legal Events

Date Code Title Description
PL Patent ceased