CH476398A - Process for producing fine etched patterns - Google Patents

Process for producing fine etched patterns

Info

Publication number
CH476398A
CH476398A CH313068A CH313068A CH476398A CH 476398 A CH476398 A CH 476398A CH 313068 A CH313068 A CH 313068A CH 313068 A CH313068 A CH 313068A CH 476398 A CH476398 A CH 476398A
Authority
CH
Switzerland
Prior art keywords
producing fine
etched patterns
fine etched
patterns
producing
Prior art date
Application number
CH313068A
Other languages
German (de)
Inventor
Forster Theodor
Mohr Theodor
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to CH313068A priority Critical patent/CH476398A/en
Priority to FR1600776D priority patent/FR1600776A/fr
Priority to DE1908901A priority patent/DE1908901C3/en
Priority to GB00804/69A priority patent/GB1255039A/en
Publication of CH476398A publication Critical patent/CH476398A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
CH313068A 1968-03-01 1968-03-01 Process for producing fine etched patterns CH476398A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CH313068A CH476398A (en) 1968-03-01 1968-03-01 Process for producing fine etched patterns
FR1600776D FR1600776A (en) 1968-03-01 1968-12-30
DE1908901A DE1908901C3 (en) 1968-03-01 1969-02-22 Process for the production of semiconductor components with small dimensions
GB00804/69A GB1255039A (en) 1968-03-01 1969-02-28 Improvements relating to the manufacture of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH313068A CH476398A (en) 1968-03-01 1968-03-01 Process for producing fine etched patterns

Publications (1)

Publication Number Publication Date
CH476398A true CH476398A (en) 1969-07-31

Family

ID=4249256

Family Applications (1)

Application Number Title Priority Date Filing Date
CH313068A CH476398A (en) 1968-03-01 1968-03-01 Process for producing fine etched patterns

Country Status (4)

Country Link
CH (1) CH476398A (en)
DE (1) DE1908901C3 (en)
FR (1) FR1600776A (en)
GB (1) GB1255039A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5157167A (en) * 1974-09-19 1976-05-19 Philips Nv
DE2134528B2 (en) * 1970-09-02 1979-04-19 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Field effect transistor, method for its production and use of the field effect transistor in an integrated circuit

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2824026A1 (en) * 1978-06-01 1979-12-20 Licentia Gmbh Barrier layer FET - mfd. by under etching bottom mask layer to cover barrier layer surface
GB2127751B (en) * 1982-10-06 1986-04-23 Plessey Co Plc Producing narrow features in electrical devices
DE3915650A1 (en) * 1989-05-12 1990-11-15 Siemens Ag Layer structuring - involving mask layer etching under photolacquer layer to obtain reduced structure width

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL143070B (en) * 1964-04-21 1974-08-15 Philips Nv PROCESS FOR APPLYING SIDE OF EACH OTHER, BY AN INTERMEDIATE SPACE OF SEPARATE METAL PARTS ON A SUBSTRATE AND OBJECT, IN PARTICULAR SEMI-CONDUCTOR DEVICE, MANUFACTURED IN APPLICATION OF THIS PROCESS.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2134528B2 (en) * 1970-09-02 1979-04-19 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Field effect transistor, method for its production and use of the field effect transistor in an integrated circuit
JPS5157167A (en) * 1974-09-19 1976-05-19 Philips Nv

Also Published As

Publication number Publication date
GB1255039A (en) 1971-11-24
DE1908901B2 (en) 1976-12-09
FR1600776A (en) 1970-07-27
DE1908901A1 (en) 1969-09-25
DE1908901C3 (en) 1981-09-24

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Legal Events

Date Code Title Description
PL Patent ceased