MX9205671A - Generacion de direccion de lectura en rafaga - Google Patents

Generacion de direccion de lectura en rafaga

Info

Publication number
MX9205671A
MX9205671A MX9205671A MX9205671A MX9205671A MX 9205671 A MX9205671 A MX 9205671A MX 9205671 A MX9205671 A MX 9205671A MX 9205671 A MX9205671 A MX 9205671A MX 9205671 A MX9205671 A MX 9205671A
Authority
MX
Mexico
Prior art keywords
rafaga
generation
reading address
address
reading
Prior art date
Application number
MX9205671A
Other languages
English (en)
Inventor
Raymond D Bowden Iii
Chester M Nibby Jr
Original Assignee
Bull Hn Information Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Syst filed Critical Bull Hn Information Syst
Publication of MX9205671A publication Critical patent/MX9205671A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
MX9205671A 1991-10-04 1992-10-02 Generacion de direccion de lectura en rafaga MX9205671A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/771,702 US5345573A (en) 1991-10-04 1991-10-04 High speed burst read address generation with high speed transfer

Publications (1)

Publication Number Publication Date
MX9205671A true MX9205671A (es) 1993-04-01

Family

ID=25092696

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9205671A MX9205671A (es) 1991-10-04 1992-10-02 Generacion de direccion de lectura en rafaga

Country Status (5)

Country Link
US (1) US5345573A (es)
EP (1) EP0535670A1 (es)
AU (1) AU660720B2 (es)
CA (1) CA2079564A1 (es)
MX (1) MX9205671A (es)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6223264B1 (en) * 1991-10-24 2001-04-24 Texas Instruments Incorporated Synchronous dynamic random access memory and data processing system using an address select signal
JPH06149662A (ja) * 1992-11-02 1994-05-31 Toshiba Corp Ｒｏｍバースト転送の連続読みだし拡大方式およびその方式を用いたｒｏｍ内蔵型マイクロコンピュータシステム
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
US5638528A (en) * 1993-11-01 1997-06-10 Motorola, Inc. Data processing system and a method for cycling longword addresses during a burst bus cycle
US5729709A (en) * 1993-11-12 1998-03-17 Intel Corporation Memory controller with burst addressing circuit
US5477488A (en) * 1994-02-14 1995-12-19 Texas Instruments Incorporated System, a memory and a process having bit processing circuits associated with memory for pre-processing data read by a processor
US5603007A (en) * 1994-03-14 1997-02-11 Apple Computer, Inc. Methods and apparatus for controlling back-to-back burst reads in a cache system
JP2982618B2 (ja) * 1994-06-28 1999-11-29 日本電気株式会社 メモリ選択回路
DE4427042C2 (de) * 1994-07-29 1997-05-22 Siemens Ag Verfahren zur Steuerung einer Sequenz von Zugriffen eines Prozessors zu einem zugeordneten Speicher
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
KR0171942B1 (ko) * 1995-06-30 1999-03-30 김주용 버스트 길이 검출 회로
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US5748914A (en) * 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
JP3748648B2 (ja) * 1996-12-19 2006-02-22 日本電気株式会社 バーストカウンター回路
US5913231A (en) * 1997-03-31 1999-06-15 International Business Machines Corporation Method and system for high speed memory address forwarding mechanism
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6343352B1 (en) 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
EP0927935A1 (en) * 1997-12-29 1999-07-07 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Memory structure with groups of memory banks and serializing means
KR100265610B1 (ko) * 1997-12-31 2000-10-02 김영환 데이터 전송속도를 증가시킨 더블 데이터 레이트 싱크로너스 디램
US6189082B1 (en) 1999-01-29 2001-02-13 Neomagic Corp. Burst access of registers at non-consecutive addresses using a mapping control word
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US7146469B2 (en) * 2002-10-24 2006-12-05 Sony Corporation Method, apparatus, and system for improving memory access speed
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
CN104238959B (zh) * 2013-06-06 2018-06-19 钰创科技股份有限公司 具有低消耗电流的内存和降低内存消耗电流的方法
CN107564563B (zh) * 2016-06-30 2020-06-09 华邦电子股份有限公司 存储器装置及其操作方法
US10411710B1 (en) * 2018-12-05 2019-09-10 Xilinx, Inc. Adaptive read scheme for configuration SRAMs in a programmable device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4366539A (en) * 1980-10-31 1982-12-28 Honeywell Information Systems Inc. Memory controller with burst mode capability
US4370712A (en) * 1980-10-31 1983-01-25 Honeywell Information Systems Inc. Memory controller with address independent burst mode capability
US5134699A (en) * 1988-06-24 1992-07-28 Advanced Micro Devices, Inc. Programmable burst data transfer apparatus and technique
US5131083A (en) * 1989-04-05 1992-07-14 Intel Corporation Method of transferring burst data in a microprocessor
US5218686A (en) * 1989-11-03 1993-06-08 Compaq Computer Corporation Combined synchronous and asynchronous memory controller
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
EP0440456B1 (en) * 1990-01-31 1997-01-08 Hewlett-Packard Company Microprocessor burst mode with external system memory

Also Published As

Publication number Publication date
CA2079564A1 (en) 1993-04-05
AU660720B2 (en) 1995-07-06
EP0535670A1 (en) 1993-04-07
US5345573A (en) 1994-09-06
AU2618592A (en) 1993-04-08

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