DE69130967T2 - Rechnerspeicheranordnung - Google Patents

Rechnerspeicheranordnung

Info

Publication number
DE69130967T2
DE69130967T2 DE69130967T DE69130967T DE69130967T2 DE 69130967 T2 DE69130967 T2 DE 69130967T2 DE 69130967 T DE69130967 T DE 69130967T DE 69130967 T DE69130967 T DE 69130967T DE 69130967 T2 DE69130967 T2 DE 69130967T2
Authority
DE
Germany
Prior art keywords
computer memory
memory arrangement
arrangement
computer
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130967T
Other languages
English (en)
Other versions
DE69130967D1 (de
Inventor
Edward C King
Forrest O Arnold
Jackson L Ellis
Robert B Moussavi
Pirmin L Weisser
Fulps V Vermeer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24249568&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69130967(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by NCR International Inc filed Critical NCR International Inc
Publication of DE69130967D1 publication Critical patent/DE69130967D1/de
Application granted granted Critical
Publication of DE69130967T2 publication Critical patent/DE69130967T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69130967T 1990-08-06 1991-07-26 Rechnerspeicheranordnung Expired - Fee Related DE69130967T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US56321490A 1990-08-06 1990-08-06

Publications (2)

Publication Number Publication Date
DE69130967D1 DE69130967D1 (de) 1999-04-15
DE69130967T2 true DE69130967T2 (de) 1999-10-21

Family

ID=24249568

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130967T Expired - Fee Related DE69130967T2 (de) 1990-08-06 1991-07-26 Rechnerspeicheranordnung

Country Status (4)

Country Link
US (1) US5953740A (de)
EP (1) EP0470735B1 (de)
JP (1) JPH04250542A (de)
DE (1) DE69130967T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761709A (en) * 1995-06-05 1998-06-02 Advanced Micro Devices, Inc. Write cache for servicing write requests within a predetermined address range
US5778422A (en) * 1996-04-04 1998-07-07 International Business Machines Corporation Data processing system memory controller that selectively caches data associated with write requests
US6199145B1 (en) * 1998-02-27 2001-03-06 Intel Corporation Configurable page closing method and apparatus for multi-port host bridges
DE10151733A1 (de) * 2001-10-19 2003-04-30 Infineon Technologies Ag Prozessor-Speicher-System
US9734059B2 (en) * 2012-11-21 2017-08-15 Advanced Micro Devices, Inc. Methods and apparatus for data cache way prediction based on classification as stack data
US9509736B2 (en) 2013-01-16 2016-11-29 Cisco Technology, Inc. Method for optimizing WAN traffic
US10565115B2 (en) 2017-03-30 2020-02-18 Western Digital Technologies, Inc. Calculating the optimal number of LBNS to prefetch per CPU

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US5043870A (en) * 1982-02-24 1991-08-27 At&T Bell Laboratories Computer with automatic mapping of memory contents into machine registers during program execution
US4719568A (en) * 1982-12-30 1988-01-12 International Business Machines Corporation Hierarchical memory system including separate cache memories for storing data and instructions
US4648030A (en) * 1983-09-22 1987-03-03 Digital Equipment Corporation Cache invalidation mechanism for multiprocessor systems
US4622631B1 (en) * 1983-12-30 1996-04-09 Recognition Int Inc Data processing system having a data coherence solution
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4783736A (en) * 1985-07-22 1988-11-08 Alliant Computer Systems Corporation Digital computer with multisection cache
US4914577A (en) * 1987-07-16 1990-04-03 Icon International, Inc. Dynamic memory management system and method
US4926317A (en) * 1987-07-24 1990-05-15 Convex Computer Corporation Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US4888679A (en) * 1988-01-11 1989-12-19 Digital Equipment Corporation Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
US5073969A (en) * 1988-08-01 1991-12-17 Intel Corporation Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal
US5283868A (en) * 1989-05-17 1994-02-01 International Business Machines Corp. Providing additional system characteristics to a data processing system through operations of an application program, transparently to the operating system

Also Published As

Publication number Publication date
EP0470735B1 (de) 1999-03-10
JPH04250542A (ja) 1992-09-07
US5953740A (en) 1999-09-14
DE69130967D1 (de) 1999-04-15
EP0470735A1 (de) 1992-02-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee