DE69131338T2 - Cache-Speicheranordnung - Google Patents

Cache-Speicheranordnung

Info

Publication number
DE69131338T2
DE69131338T2 DE69131338T DE69131338T DE69131338T2 DE 69131338 T2 DE69131338 T2 DE 69131338T2 DE 69131338 T DE69131338 T DE 69131338T DE 69131338 T DE69131338 T DE 69131338T DE 69131338 T2 DE69131338 T2 DE 69131338T2
Authority
DE
Germany
Prior art keywords
cache memory
memory arrangement
arrangement
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131338T
Other languages
English (en)
Other versions
DE69131338D1 (de
Inventor
Edward C King
Jackson L Ellis
Robert B Moussavi
Pirmin L Weisser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Application granted granted Critical
Publication of DE69131338D1 publication Critical patent/DE69131338D1/de
Publication of DE69131338T2 publication Critical patent/DE69131338T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69131338T 1990-08-06 1991-07-26 Cache-Speicheranordnung Expired - Fee Related DE69131338T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/563,216 US5835945A (en) 1990-08-06 1990-08-06 Memory system with write buffer, prefetch and internal caches

Publications (2)

Publication Number Publication Date
DE69131338D1 DE69131338D1 (de) 1999-07-22
DE69131338T2 true DE69131338T2 (de) 1999-11-25

Family

ID=24249579

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131338T Expired - Fee Related DE69131338T2 (de) 1990-08-06 1991-07-26 Cache-Speicheranordnung

Country Status (4)

Country Link
US (1) US5835945A (de)
EP (1) EP0470736B1 (de)
JP (1) JPH04250543A (de)
DE (1) DE69131338T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848432A (en) * 1993-08-05 1998-12-08 Hitachi, Ltd. Data processor with variable types of cache memories
US6317810B1 (en) * 1997-06-25 2001-11-13 Sun Microsystems, Inc. Microprocessor having a prefetch cache
US6078992A (en) * 1997-12-05 2000-06-20 Intel Corporation Dirty line cache
US6460114B1 (en) 1999-07-29 2002-10-01 Micron Technology, Inc. Storing a flushed cache line in a memory buffer of a controller
US6574707B2 (en) * 2001-05-07 2003-06-03 Motorola, Inc. Memory interface protocol using two addressing modes and method of operation
US6681292B2 (en) * 2001-08-27 2004-01-20 Intel Corporation Distributed read and write caching implementation for optimized input/output applications
US20050253858A1 (en) * 2004-05-14 2005-11-17 Takahide Ohkami Memory control system and method in which prefetch buffers are assigned uniquely to multiple burst streams
US8082396B2 (en) * 2005-04-28 2011-12-20 International Business Machines Corporation Selecting a command to send to memory
KR102523141B1 (ko) 2016-02-15 2023-04-20 삼성전자주식회사 휘발성 메모리 장치 및 불휘발성 메모리 장치를 포함하는 불휘발성 메모리 모듈

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
US4458310A (en) * 1981-10-02 1984-07-03 At&T Bell Laboratories Cache memory using a lowest priority replacement circuit
US4953073A (en) * 1986-02-06 1990-08-28 Mips Computer Systems, Inc. Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US4843542A (en) * 1986-11-12 1989-06-27 Xerox Corporation Virtual memory cache for use in multi-processing systems
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US5335336A (en) * 1988-03-28 1994-08-02 Hitachi, Ltd. Memory device having refresh mode returning previous page address for resumed page mode
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
US4933910A (en) * 1988-07-06 1990-06-12 Zenith Data Systems Corporation Method for improving the page hit ratio of a page mode main memory system
US5123095A (en) * 1989-01-17 1992-06-16 Ergo Computing, Inc. Integrated scalar and vector processors with vector addressing by the scalar processor
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
DE69025302T2 (de) * 1989-12-22 1996-10-02 Digital Equipment Corp Hochleistungsrasterpuffer- und -cachespeicheranordnung
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
US5535539A (en) * 1994-09-21 1996-07-16 Vetre; Bruce A. Fishing rod handle with extension

Also Published As

Publication number Publication date
US5835945A (en) 1998-11-10
EP0470736A1 (de) 1992-02-12
EP0470736B1 (de) 1999-06-16
JPH04250543A (ja) 1992-09-07
DE69131338D1 (de) 1999-07-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee