DE69334046D1 - Cache-Speichervorrichtung - Google Patents

Cache-Speichervorrichtung

Info

Publication number
DE69334046D1
DE69334046D1 DE69334046T DE69334046T DE69334046D1 DE 69334046 D1 DE69334046 D1 DE 69334046D1 DE 69334046 T DE69334046 T DE 69334046T DE 69334046 T DE69334046 T DE 69334046T DE 69334046 D1 DE69334046 D1 DE 69334046D1
Authority
DE
Germany
Prior art keywords
memory device
cache memory
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69334046T
Other languages
English (en)
Other versions
DE69334046T2 (de
Inventor
Oki Maki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69334046D1 publication Critical patent/DE69334046D1/de
Application granted granted Critical
Publication of DE69334046T2 publication Critical patent/DE69334046T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
DE69334046T 1992-02-28 1993-03-01 Cache-Speichervorrichtung Expired - Lifetime DE69334046T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4177492 1992-02-28
JP4177492 1992-02-28

Publications (2)

Publication Number Publication Date
DE69334046D1 true DE69334046D1 (de) 2006-08-24
DE69334046T2 DE69334046T2 (de) 2007-02-08

Family

ID=12617728

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69330875T Expired - Lifetime DE69330875T2 (de) 1992-02-28 1993-03-01 Cachespeichervorrichtung.
DE69334046T Expired - Lifetime DE69334046T2 (de) 1992-02-28 1993-03-01 Cache-Speichervorrichtung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69330875T Expired - Lifetime DE69330875T2 (de) 1992-02-28 1993-03-01 Cachespeichervorrichtung.

Country Status (5)

Country Link
US (2) US5754814A (de)
EP (2) EP0628912B1 (de)
JP (1) JP3614428B2 (de)
DE (2) DE69330875T2 (de)
WO (1) WO1993017386A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5862358A (en) * 1994-12-20 1999-01-19 Digital Equipment Corporation Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches
TW440761B (en) * 1999-05-06 2001-06-16 Ind Tech Res Inst The cache device and method
US7146469B2 (en) * 2002-10-24 2006-12-05 Sony Corporation Method, apparatus, and system for improving memory access speed

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2056134B (en) * 1977-12-22 1982-10-13 Honeywell Inf Systems Data processing system including a cache store
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
JPS615357A (ja) * 1984-06-07 1986-01-11 Fujitsu Ltd デ−タ処理装置
JPS6272041A (ja) * 1985-09-25 1987-04-02 Nec Corp キヤツシユメモリ制御装置
KR950006590B1 (ko) * 1986-11-14 1995-06-19 가부시기가이샤 히다찌세이사꾸쇼 캐시 메모리를 갖는 마이크로 프로세서
CA1300758C (en) * 1988-03-07 1992-05-12 Colin H. Cramm Mechanism for lock-up free cache operation with a remote address translation unit
JPH0778735B2 (ja) * 1988-12-05 1995-08-23 松下電器産業株式会社 キャッシュ装置と命令読出し装置
JPH0359741A (ja) * 1989-07-28 1991-03-14 Mitsubishi Electric Corp キャッシュメモリ
US5123108A (en) * 1989-09-11 1992-06-16 Wang Laboratories, Inc. Improved cpu pipeline having register file bypass and working register bypass on update/access address compare
EP0474256A3 (en) * 1990-09-07 1993-01-27 Nec Corporation In-circuit emulator
US5485589A (en) * 1991-12-31 1996-01-16 Dell Usa, L.P. Predictive addressing architecture
EP0895162A3 (de) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern

Also Published As

Publication number Publication date
EP0628912B1 (de) 2001-10-04
US5754814A (en) 1998-05-19
EP0943998A3 (de) 2000-09-13
JP3614428B2 (ja) 2005-01-26
US5634104A (en) 1997-05-27
EP0943998B1 (de) 2006-07-12
DE69330875T2 (de) 2002-04-11
WO1993017386A1 (en) 1993-09-02
DE69334046T2 (de) 2007-02-08
EP0628912A1 (de) 1994-12-14
DE69330875D1 (de) 2001-11-08
EP0943998A2 (de) 1999-09-22
EP0628912A4 (de) 1995-10-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP