KR930016798U - Jpeg 디코더에서의 어드레스 발생회로 - Google Patents

Jpeg 디코더에서의 어드레스 발생회로

Info

Publication number
KR930016798U
KR930016798U KR2019910023214U KR910023214U KR930016798U KR 930016798 U KR930016798 U KR 930016798U KR 2019910023214 U KR2019910023214 U KR 2019910023214U KR 910023214 U KR910023214 U KR 910023214U KR 930016798 U KR930016798 U KR 930016798U
Authority
KR
South Korea
Prior art keywords
generation circuit
address generation
jpeg decoder
jpeg
decoder
Prior art date
Application number
KR2019910023214U
Other languages
English (en)
Other versions
KR960005686Y1 (ko
Inventor
박정수
Original Assignee
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지전자 주식회사 filed Critical 엘지전자 주식회사
Priority to KR2019910023214U priority Critical patent/KR960005686Y1/ko
Publication of KR930016798U publication Critical patent/KR930016798U/ko
Application granted granted Critical
Publication of KR960005686Y1 publication Critical patent/KR960005686Y1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
KR2019910023214U 1991-12-21 1991-12-21 Jpeg 디코더에서의 어드레스 발생회로 KR960005686Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910023214U KR960005686Y1 (ko) 1991-12-21 1991-12-21 Jpeg 디코더에서의 어드레스 발생회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910023214U KR960005686Y1 (ko) 1991-12-21 1991-12-21 Jpeg 디코더에서의 어드레스 발생회로

Publications (2)

Publication Number Publication Date
KR930016798U true KR930016798U (ko) 1993-07-29
KR960005686Y1 KR960005686Y1 (ko) 1996-07-11

Family

ID=19325005

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910023214U KR960005686Y1 (ko) 1991-12-21 1991-12-21 Jpeg 디코더에서의 어드레스 발생회로

Country Status (1)

Country Link
KR (1) KR960005686Y1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100353894B1 (ko) * 2000-10-13 2002-09-27 (주)엠씨에스로직 제이펙 화상 데이터 버퍼링을 위한 메모리 구조 및 주소어드레스 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100353894B1 (ko) * 2000-10-13 2002-09-27 (주)엠씨에스로직 제이펙 화상 데이터 버퍼링을 위한 메모리 구조 및 주소어드레스 방법

Also Published As

Publication number Publication date
KR960005686Y1 (ko) 1996-07-11

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Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19990316

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee