KR980002967A - 3차원 소자 및 그 제조 방법 - Google Patents

3차원 소자 및 그 제조 방법 Download PDF

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Publication number
KR980002967A
KR980002967A KR1019970025986A KR19970025986A KR980002967A KR 980002967 A KR980002967 A KR 980002967A KR 1019970025986 A KR1019970025986 A KR 1019970025986A KR 19970025986 A KR19970025986 A KR 19970025986A KR 980002967 A KR980002967 A KR 980002967A
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KR
South Korea
Prior art keywords
substrate
intermediate layer
single crystal
pad
substrate surface
Prior art date
Application number
KR1019970025986A
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English (en)
Inventor
에어윈 함메를
잭 에이 만델만
베른하르트 포쉔리더
앨빈 피 쇼트
라드히카 스리니바산
라인하르트 제이 스텐글
허버트 엘 호
Original Assignee
로더리히 레테부시, 롤프 옴케
지멘스 악티엔게젤샤프트
제프리 엘. 포먼
인터내셔날 비지니스 머신스 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 로더리히 레테부시, 롤프 옴케, 지멘스 악티엔게젤샤프트, 제프리 엘. 포먼, 인터내셔날 비지니스 머신스 코포레이션 filed Critical 로더리히 레테부시, 롤프 옴케
Publication of KR980002967A publication Critical patent/KR980002967A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

제1소자위에 형성된 제2소자를 포함하는 3차원 소자 구조를 형성하기 위한 방법이 개시된다. 단결정 상부 표면을 가지는 층은 제2소자의 능동 영역을 형성하기 위한 베이스를 제공하기 위하여 제1소자상에 형성된다.

Description

3차원 소자 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 일반적 트렌치 캐패시터를 도시한 도면.
제2a도 내지 제2e도는 트렌치상의 에피테셜 실리콘층의 서로 다른 형성 단계를 도시하는 도면, 제2f도는 트렌치내의 에피 성장의 여러 가지 단계의 평면도.
제3도는 3차원 구조의 바람직한 실시예를 도시하는 도면.
제4도 내지 제5도는 3차원 DRAM 어레이를 형성하는 여러가지 단계를 도시하는 도면.

Claims (1)

  1. 비 단결정 상부 표면을 가지는 제1소자 및 능동 영역을 가지는 제2소자를 포함하는 소자 구조를 구비한 제3차원 소자를 용이하게 설계하기 위한 방법에 있어서, 단결정 구조이고 실질적을 평면의 기판 표면을 가지는 기판을 제공하는 단계를 포함하는데, 상기 기판 표면은 실질적으로 평면 패드 표면을 가지는 패드층을 포함하고 ; 제1소자의 상부 표면이 기판 표면에 함몰부를 형성하기 위하여 기판 아래에 놓이도록 상기 기판 표면에 제소자를 제조하는 단계 ; 패드 표면 이상의 높이로 함몰부에 중간층을 형성하는 단계를 포함하는데, 상기 중간층은 단결정 상부 표면을 가지며 상기 중간층의 상부 평면이 실질적으로 편평한 기판 표면을 가지도록 중간층 및 패드 표면을 평탄화하는 단계 ; 및 상기 상부 평면상에 제2소자를 제조하는 단계를 포함하고, 상기 제2소자의 능동 영역은 상부 표면내에 존재하는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970025986A 1996-06-21 1997-06-20 3차원 소자 및 그 제조 방법 KR980002967A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/667,541 1996-06-21
US08/667,541 US5792685A (en) 1996-02-22 1996-06-21 Three-dimensional device layout having a trench capacitor

Publications (1)

Publication Number Publication Date
KR980002967A true KR980002967A (ko) 1998-03-30

Family

ID=24678632

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970025986A KR980002967A (ko) 1996-06-21 1997-06-20 3차원 소자 및 그 제조 방법

Country Status (5)

Country Link
US (1) US5792685A (ko)
EP (1) EP0814507A1 (ko)
JP (1) JPH1074907A (ko)
KR (1) KR980002967A (ko)
CN (1) CN1182959A (ko)

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CN1218990A (zh) * 1997-09-05 1999-06-09 西门子公司 简化三维沟道电容器动态随机存取存储器的方法
US6383864B2 (en) * 1997-09-30 2002-05-07 Siemens Aktiengesellschaft Memory cell for dynamic random access memory (DRAM)
JPH11186514A (ja) * 1997-12-22 1999-07-09 Toshiba Corp 半導体記憶装置及びその製造方法
US6063693A (en) * 1998-03-23 2000-05-16 Telefonaktiebolaget Lm Ericsson Planar trenches
US6080618A (en) * 1998-03-31 2000-06-27 Siemens Aktiengesellschaft Controllability of a buried device layer
US6232170B1 (en) 1999-06-16 2001-05-15 International Business Machines Corporation Method of fabricating trench for SOI merged logic DRAM
US6544837B1 (en) 2000-03-17 2003-04-08 International Business Machines Corporation SOI stacked DRAM logic
US6465331B1 (en) * 2000-08-31 2002-10-15 Micron Technology, Inc. DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines
US6518118B2 (en) 2001-03-15 2003-02-11 International Business Machines Corporation Structure and process for buried bitline and single sided buried conductor formation
DE10121494A1 (de) * 2001-05-03 2002-11-14 Infineon Technologies Ag Transistor und integrierter Schaltkreis
US6894915B2 (en) * 2002-11-15 2005-05-17 Micron Technology, Inc. Method to prevent bit line capacitive coupling
US6734482B1 (en) * 2002-11-15 2004-05-11 Micron Technology, Inc. Trench buried bit line memory devices
US6724031B1 (en) 2003-01-13 2004-04-20 International Business Machines Corporation Method for preventing strap-to-strap punch through in vertical DRAMs
US7223669B2 (en) * 2004-06-16 2007-05-29 International Business Machines Corporation Structure and method for collar self-aligned to buried plate
US20060228864A1 (en) * 2005-04-12 2006-10-12 Promos Technologies Inc. Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process
US7498265B2 (en) * 2006-10-04 2009-03-03 Micron Technology, Inc. Epitaxial silicon growth
US7888723B2 (en) * 2008-01-18 2011-02-15 International Business Machines Corporation Deep trench capacitor in a SOI substrate having a laterally protruding buried strap
US8829585B2 (en) 2011-05-31 2014-09-09 International Business Machines Corporation High density memory cells using lateral epitaxy
US10699965B1 (en) 2019-02-26 2020-06-30 International Business Machines Corporation Removal of epitaxy defects in transistors
US11818877B2 (en) 2020-11-02 2023-11-14 Applied Materials, Inc. Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

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US4728623A (en) * 1986-10-03 1988-03-01 International Business Machines Corporation Fabrication method for forming a self-aligned contact window and connection in an epitaxial layer and device structures employing the method
JPS63254763A (ja) * 1987-04-10 1988-10-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
US5218218A (en) * 1990-02-01 1993-06-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
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JPH05218337A (ja) * 1992-02-04 1993-08-27 Toshiba Corp 半導体記憶装置及びその製造方法
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Also Published As

Publication number Publication date
CN1182959A (zh) 1998-05-27
US5792685A (en) 1998-08-11
EP0814507A1 (en) 1997-12-29
JPH1074907A (ja) 1998-03-17

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