WO2001099160A3 - Reduction of topography between support regions and array regions of memory devices - Google Patents

Reduction of topography between support regions and array regions of memory devices Download PDF

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Publication number
WO2001099160A3
WO2001099160A3 PCT/US2001/019684 US0119684W WO0199160A3 WO 2001099160 A3 WO2001099160 A3 WO 2001099160A3 US 0119684 W US0119684 W US 0119684W WO 0199160 A3 WO0199160 A3 WO 0199160A3
Authority
WO
WIPO (PCT)
Prior art keywords
regions
support
array
topography
reduction
Prior art date
Application number
PCT/US2001/019684
Other languages
French (fr)
Other versions
WO2001099160A2 (en
Inventor
Rainer Florian Schnabel
Carl J Radens
Howard Landis
Young Jin Park
David Kotecki
Armin M Reith
Wayne Trickle
Matthew R Wordeman
Original Assignee
Infineon Technologies Corp
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp, Ibm filed Critical Infineon Technologies Corp
Priority to EP01952175A priority Critical patent/EP1292986A2/en
Publication of WO2001099160A2 publication Critical patent/WO2001099160A2/en
Publication of WO2001099160A3 publication Critical patent/WO2001099160A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.
PCT/US2001/019684 2000-06-20 2001-06-20 Reduction of topography between support regions and array regions of memory devices WO2001099160A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01952175A EP1292986A2 (en) 2000-06-20 2001-06-20 Reduction of topography between support regions and array regions of memory devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59711400A 2000-06-20 2000-06-20
US09/597,114 2000-06-20

Publications (2)

Publication Number Publication Date
WO2001099160A2 WO2001099160A2 (en) 2001-12-27
WO2001099160A3 true WO2001099160A3 (en) 2002-10-17

Family

ID=24390138

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/019684 WO2001099160A2 (en) 2000-06-20 2001-06-20 Reduction of topography between support regions and array regions of memory devices

Country Status (3)

Country Link
EP (1) EP1292986A2 (en)
TW (1) TW494565B (en)
WO (1) WO2001099160A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050070861A (en) * 2003-12-31 2005-07-07 동부아남반도체 주식회사 Dummy layer of semiconductor device and its fabricating method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281555A (en) * 1990-11-23 1994-01-25 Hyundai Electronics Industries Co., Ltd. Method for alleviating the step difference in a semiconductor and a semiconductor device
US5345105A (en) * 1992-02-03 1994-09-06 Motorola, Inc. Structure for shielding conductors
US5689126A (en) * 1994-07-07 1997-11-18 Nec Corporation Semiconductor memory device having stacked capacitor
JPH1098166A (en) * 1996-09-20 1998-04-14 Nippon Steel Corp Semiconductor memory device and manufacture thereof
US5945702A (en) * 1996-11-19 1999-08-31 Nec Corporation Semiconductor memory device with peripheral dummy cell array
DE19935947A1 (en) * 1998-08-07 2000-02-17 Samsung Electronics Co Ltd Multilevel interconnection of a ferroelectric memory device formation method, produces interconnections of same material as ferroelectric capacitor electrodes
WO2000079587A1 (en) * 1999-06-08 2000-12-28 Infineon Technologies Ag Semiconductor storage component with storage cells, logic areas and filling structures

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281555A (en) * 1990-11-23 1994-01-25 Hyundai Electronics Industries Co., Ltd. Method for alleviating the step difference in a semiconductor and a semiconductor device
US5345105A (en) * 1992-02-03 1994-09-06 Motorola, Inc. Structure for shielding conductors
US5689126A (en) * 1994-07-07 1997-11-18 Nec Corporation Semiconductor memory device having stacked capacitor
JPH1098166A (en) * 1996-09-20 1998-04-14 Nippon Steel Corp Semiconductor memory device and manufacture thereof
US5945702A (en) * 1996-11-19 1999-08-31 Nec Corporation Semiconductor memory device with peripheral dummy cell array
DE19935947A1 (en) * 1998-08-07 2000-02-17 Samsung Electronics Co Ltd Multilevel interconnection of a ferroelectric memory device formation method, produces interconnections of same material as ferroelectric capacitor electrodes
WO2000079587A1 (en) * 1999-06-08 2000-12-28 Infineon Technologies Ag Semiconductor storage component with storage cells, logic areas and filling structures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 09 31 July 1998 (1998-07-31) *

Also Published As

Publication number Publication date
EP1292986A2 (en) 2003-03-19
WO2001099160A2 (en) 2001-12-27
TW494565B (en) 2002-07-11

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