WO2002045158A3 - Memory cell with vertical floating gate transistor - Google Patents

Memory cell with vertical floating gate transistor Download PDF

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Publication number
WO2002045158A3
WO2002045158A3 PCT/US2001/043903 US0143903W WO0245158A3 WO 2002045158 A3 WO2002045158 A3 WO 2002045158A3 US 0143903 W US0143903 W US 0143903W WO 0245158 A3 WO0245158 A3 WO 0245158A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
center portion
memory cell
conductor
gate transistor
Prior art date
Application number
PCT/US2001/043903
Other languages
French (fr)
Other versions
WO2002045158A2 (en
Inventor
Daniele Casarotto
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Priority to EP01987070A priority Critical patent/EP1344250A2/en
Publication of WO2002045158A2 publication Critical patent/WO2002045158A2/en
Publication of WO2002045158A3 publication Critical patent/WO2002045158A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor device (8) includes a substrate (10) having a trench (18) formed therein. A gate structure for a vertical transistor is formed adjacent to a sidewall of the trench. The gate structure includes a floating gate conductor (52) formed in contact with sidewalls of the trench. The floating gate forms a void in a center portion of the floating gate conductor, and the center portion has vertically disposed surfaces. A dielectric layer (46) lines the void in the center portion of the floating gate conductor, and a control gate (48) conductor is formed in contact with the dielectric layer. The control gate conductor fills the void in the center portion of the floating gate conductor. Methods for fabricating the semiconductor device are also disclosed.
PCT/US2001/043903 2000-12-01 2001-11-14 Memory cell with vertical floating gate transistor WO2002045158A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01987070A EP1344250A2 (en) 2000-12-01 2001-11-14 Memory cell with vertical floating gate transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72795500A 2000-12-01 2000-12-01
US09/727,955 2000-12-01

Publications (2)

Publication Number Publication Date
WO2002045158A2 WO2002045158A2 (en) 2002-06-06
WO2002045158A3 true WO2002045158A3 (en) 2003-05-01

Family

ID=24924804

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043903 WO2002045158A2 (en) 2000-12-01 2001-11-14 Memory cell with vertical floating gate transistor

Country Status (2)

Country Link
EP (1) EP1344250A2 (en)
WO (1) WO2002045158A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461182B2 (en) 2007-05-07 2016-10-04 Infineon Technologies Ag Memory cell

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049956A (en) * 1989-07-13 1991-09-17 Kabushiki Kaisha Toshiba Memory cell structure of semiconductor memory device
US5616510A (en) * 1992-11-02 1997-04-01 Wong; Chun C. D. Method for making multimedia storage system with highly compact memory cells
DE19808182C1 (en) * 1998-02-26 1999-08-12 Siemens Ag Electrically programmable memory cell arrangement
US6093606A (en) * 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049956A (en) * 1989-07-13 1991-09-17 Kabushiki Kaisha Toshiba Memory cell structure of semiconductor memory device
US5616510A (en) * 1992-11-02 1997-04-01 Wong; Chun C. D. Method for making multimedia storage system with highly compact memory cells
DE19808182C1 (en) * 1998-02-26 1999-08-12 Siemens Ag Electrically programmable memory cell arrangement
US6093606A (en) * 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device

Also Published As

Publication number Publication date
WO2002045158A2 (en) 2002-06-06
EP1344250A2 (en) 2003-09-17

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