WO2002045158A2 - Memory cell with vertical floating gate transistor - Google Patents
Memory cell with vertical floating gate transistor Download PDFInfo
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- WO2002045158A2 WO2002045158A2 PCT/US2001/043903 US0143903W WO0245158A2 WO 2002045158 A2 WO2002045158 A2 WO 2002045158A2 US 0143903 W US0143903 W US 0143903W WO 0245158 A2 WO0245158 A2 WO 0245158A2
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- 230000015654 memory Effects 0.000 title claims description 36
- 239000004020 conductor Substances 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000011800 void material Substances 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 description 30
- 238000009792 diffusion process Methods 0.000 description 24
- 239000000463 material Substances 0.000 description 21
- 238000002955 isolation Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 239000007943 implant Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 206010010144 Completed suicide Diseases 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- This disclosure relates to semiconductor structures and fabrication methods, and more particularly, to memory cells and methods for fabrication of memory cells with floating gates which are independent of lithographic scaling.
- Semiconductor memories such as flash memories include lithographically patterned features.
- the current lithographic processes dictate the smallest feature size (F) possible for line structures formed in the semiconductor fabrication process.
- F feature size
- the desire to shrink chip sizes and increases in layout density have caused improved lithographic resolution.
- This lithographic resolution improvement has lead to smaller structural components, which are formed on a semiconductor device.
- smaller features led to other problems. For example, shorter channels are subject to short channel effects.
- One solution for conserving layout area on a chip may include the formation of vertical devices, e.g., transistors.
- the length of the transistor channel for example, can extend deep into a semiconductor substrate.
- a floating gate activates transistors.
- the floating gate is capacitively coupled to a wordline so that when the wordline is activated, the floating gate can cause conduction through a channel of the transistor.
- the floating gate and the wordline function as capacitor plates. It is advantageous to have the largest possible cross-sectional area between the plates of a capacitor to ensure the best possible capacitive coupling. However, due to lithographic processing limitations less than desirable capacitive coupling is experienced since the cross-sectional area is limited.
- a method for fabricating a semiconductor device includes forming a trench in a semiconductor substrate and depositing a first conductive material in the trench.
- the first conductive material is etched in the trench to remove a portion of the first conductive material such that the first conductive material includes vertically disposed interior surfaces and remains in contact with sidewalls of the trench to form a floating gate conductor.
- a dielectric layer is deposited over the interior surfaces of the first conductive material, and a second conductive material is deposited over the dielectric layer to fill the trench to form a control gate conductor for capacitively coupling to the floating gate conductor.
- the interior surfaces of the first conductive material may include a circular cross-section or a rectangular cross-section in a plane parallel to a major surface of the substrate.
- the step of etching may include performing a spacer etch to remove the portion of the first conductive material.
- the step of depositing a dielectric layer may include depositing a dielectric layer including ONO .
- the method preferably includes the step of forming a gate oxide on the sidewalls of the trench.
- a vertical transistor channel is preferably formed in the substrate adjacent to the trench and the method preferably includes the step of forming a gate oxide on the sidewalls of the trench such that when the floating gate is activated conduction occurs through the channel .
- the method may include the step of forming a wordline in electrical contact with the control gate conductor.
- a semiconductor device of the present invention includes a substrate having a trench formed therein and a gate structure for a vertical transistor formed adjacent to a sidewall of the trench.
- the gate structure includes a floating gate conductor formed in contact with sidewalls of the trench and forming a void in a center portion of the floating gate conductor, the center portion having vertically disposed surfaces.
- a dielectric layer lines the void in the center portion of the floating gate conductor, and a control gate conductor is formed in contact with the dielectric layer and fills the void in the center portion of the floating gate conductor.
- the trench preferably includes a gate dielectric formed on the sidewalls thereof.
- the vertical transistor may include a vertical channel disposed adjacent to the trench, the vertical channel conducting when activated by the floating gate conductor.
- the vertical channel preferably connects a source region to a vertically offset drain region when activated by the floating gate conductor.
- One of the source region and the drain region are connected to a bit line by a contact .
- the source region or the drain region, and the contact are shared by two adjacent vertical transistors.
- the control gate conductor is preferably electrically connected to a wordline.
- the floating gate conductor may include a circular cross-section or a rectangular cross-section in a plane parallel to a major surface of the substrate.
- Another semiconductor device of the present invention includes a substrate having a trench formed therein and a gate structure for a vertical transistor formed adjacent to a sidewall of the trench.
- the gate structure occupies a layout area including one of a length or width of a groundrule size, F.
- the gate structure further includes a floating gate conductor formed in the trench in contact with sidewalls of the trench and forming a void in a center portion of the floating gate conductor, the center portion having vertically disposed surfaces.
- a dielectric layer lines the void in the center portion of the floating gate conductor, and a control gate conductor is formed in contact with the dielectric layer and fills the void in the center portion of the floating gate conductor such that a surface area between the control gate and the floating gate is greater than F 2 .
- the trench preferably includes a gate dielectric formed on the sidewalls thereof.
- the vertical transistor may include a vertical channel disposed adjacent to the trench, the vertical channel conducting when activated by the floating gate conductor.
- the vertical channel preferably connects a source region to a vertically offset drain region when activated by the floating gate conductor.
- the source region or the drain region is connected to a bit line by a contact .
- the source region or the drain region and the contact are shared by two adjacent vertical transistors.
- the control gate conductor is preferably electrically connected to a wordline.
- the floating gate conductor may include a rectangular cross-section or a circular cross-section in a plane parallel to a major surface of the substrate.
- the gate structure occupies a layout area including both a length and width of about a groundrule size, F.
- the gate structure occupies a layout area equal to the layout area occupied by the trench; however the contact gate and the floating gate have a common surface area of greater than F 2 .
- a memory cell, which includes the gate structure, may occupy a layout area of about 4F 2 .
- FIG. 1 is a top schematic view showing the orientation and position of diffusion regions formed in a substrate of a semiconductor device in accordance with one embodiment of the present invention
- FIG. 2 is a cross-sectional view taken at section line 2-
- FIG. 3 is a cross-sectional view taken at section line 3-
- FIG. 3 of FIG. 1 showing trenches filled after forming the diffusion regions in accordance with the present invention
- FIG. 4 is a cross-sectional view taken at section line 4-
- FIG. 4 of FIG. 5 showing of the semiconductor device of FIG. 2 after isolation regions are formed in accordance with the present invention
- FIG. 5 is a top layout view showing the isolation regions formed in accordance with one embodiment of the present invention
- FIG. 6 is a cross-sectional view taken at section line 6- 6 of FIG. 5 after isolation regions are formed in accordance with the present invention
- FIG. 7 is a magnified cross-sectional view of the semiconductor device of FIG. 4 showing the formation of a gate dielectric and a trench top dielectric in accordance with the present invention
- FIG. 8 is a magnified cross-sectional view of the semiconductor device of FIG. 7 showing the formation of a floating gate conductor by a spacer etch process in accordance with the present invention
- FIG. 9A is a cross-sectional view of the semiconductor device of FIG. 8 showing the formation of a control gate conductor in accordance with the present invention.
- FIG. 9B is a magnified cross-sectional view of the semiconductor device of FIG. 9A showing the formation of a control gate conductor in accordance with the present invention
- FIG. 10 is a cross-sectional view taken at section line 10-10 of FIG. 9A showing a memory array in a top view in accordance with the present invention
- FIG. 11 is a cross-sectional view taken along the plane section line 11-11 of FIG. 10 in accordance with the present inven ion;
- FIG. 12 is a cross-sectional view taken at section line 12-12 of FIG. 13 after a gate stack, contacts and a bitline are formed in accordance with the present invention
- FIG. 13 is a top layout view with layers removed so that gate stacks may be viewed in accordance with the present invention
- FIG. 14 is a cross-sectional view taken at section line 14-14 of FIG. 13 in accordance with the present invention.
- FIG. 15 is a top schematic view showing the orientation and position of diffusion regions formed in a substrate of a semiconductor device in accordance with another embodiment of the present invention.
- FIG. 16 is a cross-sectional view taken at section line 16-16 of FIG. 15 showing trenches and diffusion regions formed in accordance with the present invention
- FIG. 17 is a cross-sectional view taken at section line 17-17 of FIG. 15 showing trenches and diffusion regions formed in accordance with the present invention
- FIG. 18 is a cross-sectional view taken at section line 18-18 of FIG. 19 showing of the semiconductor device of FIG. 16 after formation of floating and control gate conductors in accordance with the present invention
- FIG. 19 is a top layout view showing floating and control gate structures extending longitudinally down along the semiconductor device in accordance with the present invention.
- FIG. 20 is a cross-sectional view taken at section line 20-20 of FIG. 19 showing a control gate formed in accordance with the present invention
- FIG. 21 is a top layout view showing isolation regions formed perpendicularly to the gate structures of FIG. 19 in accordance with the present invention
- FIG. 22 is a cross-sectional view taken at section line 22-22 of FIG. 21 gate structures formed in accordance with the present invention.
- FIG. 23 is a cross-sectional view taken at section line 23-23 of FIG. 21 showing isolation regions in accordance with the present invention
- FIG. 24 is a cross-sectional view taken at section line 24-24 of FIG. 25 after a gate stack, contacts and a bitline are formed in accordance with the present invention
- FIG. 25 is a top layout view with layers removed so that gate structures may be viewed in accordance with the present invention.
- FIG. 26 is a cross-sectional view taken at section line 26-26 of FIG. 25 showing isolation regions formed in accordance with the present invention.
- the present invention includes memory cells and methods for fabrication wherein a floating gate is independent of lithographic scaling.
- the present invention will be illustratively described in terms of flash memory cells and fabrication methods. However, the present invention is broader and is applicable to any semiconductor device, which can benefit from reduced layout area and increased channel length for transistors formed thereon.
- the present invention may include bitline contacts shared between every 2 cells for lower bitline capacitance.
- a very high capacitive coupling between a control (e.g., wordline) and a floating gate is achieved.
- a more uniform cell structure is provided where the gate structures are formed in a trench, which extends across the memory array.
- FIG. 1 a top view of a substrate 10 is shown indicating diffusion regions 12. Diffusion regions 12 are shown to illustrate their orientation and to indicate cross-sectional directions for FIGS. 2 and 3.
- Substrate 10 is preferably a semiconductor substrate, such as, for example, a doped monocrystalline silicon, although other substrate materials may be employed.
- Substrate 10 is preferably part of a memory array for a memory device 8.
- Memory device 8 may be any memory device having a floating gate structure.
- device 8 includes a flash memory device, such as for example, an electrically erasable nonvolatile memory. Other programmable memories are also contemplated.
- the fabrication of a 4F 2 area memory cell will be illustratively described to demonstrate one aspect of the present invention.
- Dimension arrows "D" will be indicated throughout the views to illustratively demonstrate a groundrule dimension or minimum feature size dimension F. Each double-headed arrow D will illustratively indicate F.
- other memory cell areas may be realized in accordance with the present invention.
- substrate 10 is subjected to an oxidation process to form a pad oxide layer 14.
- Pad oxide 14 is covered by a dielectric layer 16, such as for example, a nitride layer (e.g., pad nitride) .
- a hardmask layer (not shown) is formed on layer 16, followed by the patterning of a lithographic mask (not shown) .
- the lithographic mask is employed to pattern the hardmask by known etching methods.
- Hardmask is then employed to etch dielectric layer 16, pad oxide 14 and substrate 10 to form trenches 18.
- Diffusion regions 12 are formed by a known implanting process (e.g., N- type dopant implant) . Diffusion regions 12 form source lines for vertical transistors, which will be described in greater detail below.
- the hardmask is removed, and a buffer oxidation process is performed to form an oxide 20 on surfaces within trenches 18.
- Trenches 18 are filled with a material 22, preferably polysilicon, by a deposition process.
- Material 22 is planarized by, for example, a chemical-mechanical polishing process to provide top surface 24.
- Dielectric layer 14 is now removed .
- a dielectric layer 26, for example a nitride layer, is deposited and patterned (See FIG. 5) by employing a hardmask (e.g., a TEOS hardmask) and a lithographic process (not shown) .
- Isolation trenches 28 are etched in accordance with the hardmask employed to pattern layer 26. Isolation trenches 28 are preferable etched by an anisotropic etching process, such as for example, reactive ion etching.
- the hardmask is removed, and a dielectric material 30 is deposited to fill trenches 28.
- Dielectric material 30 may include an oxide, and more preferably, a high density plasma (HDP) deposited oxide.
- a chemical-mechanical polish (CMP) process is performed to planarize dielectric material 30 down to dielectric layer 26, and trench isolation regions 32 are formed .
- CMP chemical-mechanical polish
- FIGS. 5 and 6 a top view (FIG. 5) of the memory array of device 8 is shown after planarization of material 30 to form isolation regions 32.
- FIG. 6 shows a cross-sectional view of a section indicated in FIG. 5, which is perpendicular to the section of FIG. 4. Dielectric layer 26 is now removed.
- a doping mask layer (not shown) is formed over device 8 and pattered to permit doping of substrate 10 between trenches 18.
- One or more known implantation processes may be employed to form diffusion regions 34, which will function as a drain for a vertical transistor as will be explained below.
- the doping mask layer is now removed and material 22 is removed from trenches 18.
- a dielectric layer 38 is formed on horizontal surfaces, preferably an oxide formed by a high density plasma (HDP) oxidation process. Layer 38 may be referred to as a trench top oxide (TTO) . Vertical sidewalls of trenches 18 are oxidized to form a gate oxide 40 thereon.
- HDP high density plasma
- a conductive material 42 such as a polysilicon film, is conformally deposited in trenches 18.
- a spacer etch process is performed to leave a spacer from material 42, which lines sidewalls of trench 18.
- a center .region 44 does not include material 42.
- the spacer etch process includes an anisotropic etch process, such as reactive ion etching (RIE) .
- RIE is tuned to etch the thickness of the layer of conductive material 42 to thereby leave spacers 42.
- Other processes may also be employed to form conductive material, which lines the sidewalls of trench 18.
- a dielectric layer 46 is deposited over exposed surfaces of material 42.
- Layer 46 will function as a capacitor dielectric between material 42 (which forms a floating gate in accordance with the invention) and a control gate 48.
- Layer 46 may include a nitride, such as silicon nitride and preferably a layer of 0N0 (silicon oxide, silicon nitride, silicon oxide) . If ONO is employed, a thickness for layer 46 may be between 10 to 20 nm.
- a conductive material 50 is deposited over layer 46. Material 50 preferably includes polysilicon. Material 50 is planarized (e.g., by CMP) down to layer 46 (or layer 38). Material 50 forms control gate 48. Control gate 48 and floating gate 52 function as capacitor plates separated by layer 46.
- the memory array is processed along with a support region (not shown) .
- a silicon nitride liner 54 is formed over device 8.
- the array region and support region are masked.
- the support region mask is opened and liner 54 is etched in the support region followed by support processing (e.g., sacrificial oxidation, implants, gate oxidation, polysilicon deposition and/or other known processes) .
- support processing e.g., sacrificial oxidation, implants, gate oxidation, polysilicon deposition and/or other known processes.
- the polysilicon layer employed in processing the support region is removed from the array region followed by deglazing liner 54 and the removal of liner 54 from the array region.
- FIG. 10 is a cross- sectional view taken at section line 10-10 of FIG. 9A.
- FIG. 10 shows floating gate 52 and control gate 48 having layer 46 disposed therebetween.
- the surface area between gates 48 and 52 is increased by at least one order of magnitude over conventional floating gates, which typically occupy IF 2 in area.
- the surface area between gates 48 and 52 occupies a three dimensional space in a conical or cylindrical configuration. This configuration can extend deep into substrate 10 and is virtually unlimited in terms of surface area between gates 48 and 52.
- FIG. 11 shows a cross- section taken along the direction of section line 11-11 in FIG. 10.
- gate stacks 60 are formed by depositing and patterning a conductive layer or conductive layers in electrical contact with control gate 48.
- a layer 62 may include polysilicon (e.g., heavily doped) and a high conductivity layer 64 (e.g., Tungsten, Tungsten suicide, or other highly conductive material) .
- a dielectric cap 66 and spacers 68 are provided to isolate gate stack 60 from contacts 70. Contacts 70 are formed through a dielectric layer 72, which may be formed from silicon dioxide. Holes for contacts 70 need to be formed through dielectric layer 72, layer 46 and layer 38 to make contact to diffusion region 34.
- a conductive line 74 is formed to provide access to vertical transistors 76. When gate stack 60 (wordline) is activated conduction is achieved through transistor 76 between diffusion region 12 and line 74.
- Transistors 76 are created along the side of trench 18 in substrate 10.
- the source junction (12) is implanted through the trench bottom and creates a buried conductive path across the array. Overlap of a source junction 12 and a vertical floating gate 46 provides an interface for electrical erasing (e.g., when a source erase is employed) .
- the floating gate 52 is created by deposition and a spacer etch, forming a spacer structure in the trench.
- the control gate 48 is deposited after dielectric layer 46 deposition on floating gate 52 and provides electrical contact to the wordline (gate stack 60) .
- the drain junction (34) is formed by an implantation step at the active area surface and is connected to line 74 (e.g., bit line) through contacts 74.
- line 74 e.g., bit line
- each contact 74 (and drain region 34) services two adjacent memory cells.
- the source and drain regions may be reversed, or may include conductive regions such as storage nodes, conductive lines or other devices or structures.
- FIGS. 13 and 14 a top layout of device 8 is schematically shown with an outline of layer 46 for reference. Note that arrows " D" indicate a 4F 2 or less area memory cell in accordance with the invention.
- the present invention provides a substantial increases in floating gate to control gate surface area while maintaining a small (e.g., 4F 2 or less) memory cell area.
- FIG. 14 shows a cross-section taken along the direction of section line 14-14 in FIG. 13.
- substrate 10 is shown indicating diffusion regions 13. Diffusion regions 13 are shown to illustrate their orientation and to indicate cross- sectional directions for FIGS. 16 and 17.
- Substrate 10 is preferably a semiconductor substrate, such as, for example, a doped monocrystalline silicon, although other substrate materials may be employed.
- Substrate 10 is preferably part of a memory array for a memory device 9.
- Memory device 9 may be any memory device having a floating gate structure.
- device 9 includes a flash memory device, such as for example, an electrically erasable nonvolatile memory. Other programmable memories are also contemplated.
- substrate 10 is subjected to an oxidation process to form a pad oxide layer 14.
- Pad oxide 14 is covered by a dielectric layer 16, such as for example, a nitride layer (e.g., pad nitride) .
- a hardmask layer 15 is formed on layer 16 and patterned by lithography. Hardmask 15 is then employed to etch dielectric layer 16, pad oxide 14 and substrate 10 to form trenches 18, which extend longitudinally across at least a portion of device 9.
- Diffusion regions 13 are formed by a known implanting process (e.g., N-type dopant implant) .
- Diffusion regions 13 form source lines for vertical transistors, which extend longitudinally in accordance with trenches 18.
- the hardmask 15 is removed, and a buffer oxidation process is performed to form an oxide 20 on surfaces within trenches 18. Hardmask 15 and dielectric layer 14 are now removed.
- a doping mask layer (not shown) is formed over device 9 and pattered to permit doping of substrate 10 between trenches 18.
- One or more known implantation processes may be employed to form diffusion regions 34, which will function as a drain for a vertical transistor as will be explained below.
- the doping mask layer is now removed.
- a dielectric layer 38 is formed on horizontal surfaces, preferably an oxide formed by a high density plasma (HDP) oxidation process, which preferentially forms on horizontal surfaces. Layer 38 may be referred to as a trench top oxide (TTO) .
- TTO trench top oxide
- Trenches 18 are lined with a conductive material 42, preferably polysilicon, by a deposition process.
- a spacer etch process is performed to leave a spacer from material 42, which lines sidewalls of trench 18.
- a center region 44 does not include material 42.
- the spacer etch process includes an anisotropic etch process, such as reactive ion etching (RIE) .
- RIE is tuned to etch the thickness of the layer of conductive material 42 to thereby leave spacers (floating gate 52) .
- a dielectric layer 46 is deposited over exposed surfaces of material 42.
- Layer 46 will function as a capacitor dielectric between material 42 (which forms a floating gate in accordance with the invention) and a control gate 48.
- Layer 46 may include a nitride, such as silicon nitride and preferably a layer of ONO (silicon oxide, silicon nitride, silicon oxide) . If ONO is employed, a thickness for layer 46 may be between 10 to 20 nm.
- a conductive material 50' is deposited over layer 46. Material 50 preferably includes polysilicon. Material 50 is planarized (e.g., by CMP) down to layer 38 (or layer 46) . Material 50 forms a control gate 48.
- Control gate 48 and floating gate 52 function as capacitor plates separated by layer 46.
- FIGS. 19 and 20 a top view of the memory array of device 9 is shown in FIG. 19 after planarization of material 50.
- Floating gates 52 and control gates 48 extend longitudinally along direction "A" on device 9.
- FIG. 20 shows a cross-sectional view of a section indicated in FIG. 19, which is perpendicular to the section of FIG. 18.
- Layer 26 is not shown in FIG. 21, for clarity.
- Isolation trenches 28 are etched in accordance with the hardmask employed to pattern layer 26.
- Isolation trenches 28 are preferably etched by an anisotropic etching process, such as for example, reactive ion etching.
- the hardmask is removed, and a dielectric material 30 is deposited to fill trenches 28.
- Dielectric material 30 may include an oxide, and preferably, a high density plasma (HDP) deposited oxide.
- a CMP process is performed to planarize dielectric material 30 down to dielectric layer 26, and trench isolation regions 32 are formed.
- the memory array is processed along with a support region (not shown) .
- a silicon nitride liner (not shown) is formed over device 9.
- the array region and support region are masked.
- the support region mask is opened followed by support processing (e.g., sacrificial oxidation, implants, gate oxidation, polysilicon deposition and/or other known processes) .
- the polysilicon layer employed in processing the support region is removed from the array region followed by deglazing liner 54 (see e.g., FIG. 9A) and the removal of liner 54 from the array region.
- a gate stack 60 is formed by depositing and patterning a conductive layer or conductive layers in electrical contact with control gate 48.
- a layer 62 may include polysilicon (e.g., heavily doped) and a high conductivity layer 64 (e.g., Tungsten, Tungsten suicide, or other highly conductive material) .
- a dielectric cap 66 and spacers 68 are provided to isolate gate stack 60 from contacts 70. Contacts 70 are formed through a dielectric layer 72, which may be formed from silicon dioxide. Holes for contacts 70 need to be formed through dielectric layer 72, layer 46 and layer 38 to make contact to diffusion region 34.
- a conductive line 74 is formed to provide access to a vertical transistor 76. When gate stack 60 (wordline) is activated conduction is achieved through transistor 76 between diffusion region 13 and line 74.
- Transistor 76 is created along the side of trenches 18 in substrate 10.
- the source junction (13) is implanted through the trench bottom and creates a buried conductive path across the array.
- the floating gate 52 is created by deposition and a spacer etch, forming a spacer structure in the trench.
- the control gate 48 is deposited after dielectric layer 46 deposition on floating gate 52 and provides electrical contact to the wordline (gate stack 60) .
- the drain junction (34) is formed by an implantation step at the active area surface and is connected to line 74 (e.g., bit line) through contacts 70.
- each contact 70 (and drain region 34) services two adjacent memory cells.
- the surface area between gates 48 and 52 is increased by at least one order of magnitude over conventional floating gates, which typically occupy IF 2 in area.
- the surface area between gates 48 and 52 occupies a three dimensional space in a conical or cylindrical configuration. This configuration can extend deep into substrate 10 and is virtually unlimited in terms of surface area between gates 48 and 52.
- FIGS. 25 and 26 a top layout (FIG. 25) of device 9 is schematically shown with layer 72 and line 74 not shown for clarity. Note that arrows "D" indicate a 4F 2 or less area memory cell in accordance with the invention.
- the present invention provides a substantial increase in floating gate to control gate surface area while maintaining a small (e.g., 4F 2 or less) memory cell area.
- FIG. 26 shows a cross- section taken along the direction of section line 26-26 in FIG. 25.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01987070A EP1344250A2 (en) | 2000-12-01 | 2001-11-14 | Memory cell with vertical floating gate transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US72795500A | 2000-12-01 | 2000-12-01 | |
US09/727,955 | 2000-12-01 |
Publications (2)
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WO2002045158A2 true WO2002045158A2 (en) | 2002-06-06 |
WO2002045158A3 WO2002045158A3 (en) | 2003-05-01 |
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PCT/US2001/043903 WO2002045158A2 (en) | 2000-12-01 | 2001-11-14 | Memory cell with vertical floating gate transistor |
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EP (1) | EP1344250A2 (en) |
WO (1) | WO2002045158A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9461182B2 (en) | 2007-05-07 | 2016-10-04 | Infineon Technologies Ag | Memory cell |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5049956A (en) * | 1989-07-13 | 1991-09-17 | Kabushiki Kaisha Toshiba | Memory cell structure of semiconductor memory device |
US5616510A (en) * | 1992-11-02 | 1997-04-01 | Wong; Chun C. D. | Method for making multimedia storage system with highly compact memory cells |
DE19808182C1 (en) * | 1998-02-26 | 1999-08-12 | Siemens Ag | Electrically programmable memory cell arrangement |
US6093606A (en) * | 1998-03-05 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Method of manufacture of vertical stacked gate flash memory device |
-
2001
- 2001-11-14 EP EP01987070A patent/EP1344250A2/en not_active Withdrawn
- 2001-11-14 WO PCT/US2001/043903 patent/WO2002045158A2/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5049956A (en) * | 1989-07-13 | 1991-09-17 | Kabushiki Kaisha Toshiba | Memory cell structure of semiconductor memory device |
US5616510A (en) * | 1992-11-02 | 1997-04-01 | Wong; Chun C. D. | Method for making multimedia storage system with highly compact memory cells |
DE19808182C1 (en) * | 1998-02-26 | 1999-08-12 | Siemens Ag | Electrically programmable memory cell arrangement |
US6093606A (en) * | 1998-03-05 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Method of manufacture of vertical stacked gate flash memory device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9461182B2 (en) | 2007-05-07 | 2016-10-04 | Infineon Technologies Ag | Memory cell |
DE102008021396B4 (en) | 2007-05-07 | 2019-12-05 | Infineon Technologies Ag | Memory cell, memory cell array and method of manufacturing a memory cell |
Also Published As
Publication number | Publication date |
---|---|
EP1344250A2 (en) | 2003-09-17 |
WO2002045158A3 (en) | 2003-05-01 |
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