TW494565B - Reduction of topography between support regions and array regions of memory devices - Google Patents

Abstract

A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.

Description

1. V. Description of the Invention (Background of the Invention 1. TECHNICAL FIELD The present disclosure relates to semiconductor manufacturing, and more particularly, to a device and method including an array structure formed in a memory device support area to reduce the topology therebetween. 2 • Summary of related technologies Generally speaking, memory devices and especially dynamic random access memories (fRAMs) include a structure formed by two main parts: a transistor, a capacitor, and the smallest amplifier circuit. The array of memory cells, and 2) a large support area (generally about 20-40 / 0 of the total chip area) to supply power, Buy write control logic, repetitive circuits, and other circuits needed to operate the memory device. In the case of a stacked acoustic capacitor, the capacitor is formed by a stack, and the thickness is generally about 15 microns, including a lower electrode (EL), a dielectric medium, and a higher common electrode plate (pL ). This stack is usually formed after the first metal (bit line level) but before other metallization levels. Due to the height of the capacitor stack, the fact that there are no electrodes in the support area can result in a significant topology at the edge of the array. Referring to FIG. 1, a partial cross-sectional view of a semiconductor memory device 10 is shown. The semiconductor device 10 includes a stacked capacitor structure or stack 12 formed in an array region 14. The stack 12 includes a lower electrode 16, a dielectric medium or valley dielectric 18, and a higher common electrode plate 20. A support area 22 is included on the device 10, and this area includes a support circuit for operating the device 10. The support area 22 shows a part of the first metal layer 24. This area and the array area 494565 A7 B7 V. Description of the invention

The bit lines 26 in the field 14 are formed simultaneously. A dielectric layer 28 is formed on the stack 12 and the support region 22 in the array region 14. The channel 25 that is protruded down to the metal line 24 is formed through the dielectric layer 28. Form a topology feature or topology 30. At the level of subsequent processing, Topology 30 disturbs the definition and formation of the characteristics of critical regions. This effect is significant at the edges of the array region 14 and can be enhanced by the topology of the first metal layer 24 below. This effect is a major cause of memory cell failure and component reliability problems at the edge of the array area 14. Therefore, there is a need for a method capable of reducing the topology between an array region and a support region of a semiconductor memory device. There is still a need for an improved layout method capable of minimizing an interface between an array region and a support region of a semiconductor memory device. SUMMARY OF THE INVENTION A semiconductor device according to the present invention includes a substrate whose main surface includes an array region and a support region. The array region includes a memory cell structure 'whose first height exceeds the major surface of the substrate. The support area includes a virtual structure formed therein with a second height exceeding the main surface. A dielectric layer is formed on the memory cell structure in the array area and the virtual structure of the support area, so that the upper surface of the dielectric layer is substantially flat. The topological characteristics of the dielectric layer supporting this domain. -In an alternative embodiment, the memory cell may include a stacked capacitor ' and the virtual structure may include at least a portion of the components for the stacked capacitor. The present invention preferably uses a topology between a support area and an array area.

And then reduce y to the minimum characteristic size less than 丨 0 times. The dummy structure may include one of a dielectric material and a conductive material. The dummy structure may include at least one of a lower stacked plutonium capacitor electrode and a higher stacked capacitor electrode. Through the virtual structure capable of gradually lowering the height exceeding the main surface, the dielectric ^ σ gradually changes between the array region J and the support region. The virtual structures may be spaced from each other to a minimum characteristic size of about i to about 20 with special technology. The dummy structure may include a conductive material, and the dummy structure is preferably electrically floating to avoid grounding. The virtual structure may be tied to a common ground or to a -solid potential relative to ground. The second height depends on the position within the support area. The semiconductor device further includes a plurality of first metal lines arranged in a first direction in the supporting area; and a plurality of second metal lines arranged in a layer different from the first metal lines, and the second metal The lines are substantially perpendicular to the second direction, and the virtual structure is preferably designed such that the adjacent first metal lines and the first metal lines do not overlap the same virtual structure. The first height and the second height are preferably substantially equal. Another semiconductor memory device according to the present invention includes a substrate whose main surface includes an array region and a support region. The array region includes a memory cell structure, a first height of which exceeds the main surface of the substrate, and the support region includes a conductive structure formed therein with a second height exceeding the principal surface. The supporting circuit in the supporting area adopts a conductive structure. A dielectric layer is formed on the memory cell structure in the array region and the conductive structure in the support region, so that the upper surface of the dielectric layer is substantially flat, which substantially reduces across the array region and Introduction of this support area-6- This paper size is suitable for financial and family care (CNS) A4 specification (21Gx297 public love) A7

Topological characteristics of the electrical layer. In alternative embodiments, the memory cell may include a stacked capacitor device and the conductive structure may include at least part of the elements used by the stacked capacitor. The conductive structure may include at least a lower stacked capacitor electrode and a stacked capacitor electrode. By gradually reducing the height of the conductive and dielectric structures on the major surface, the dielectric layer can gradually change between the array region and the support region. The virtual structure can be grounded together or connected to a fixed potential relative to ground. The present invention preferably reduces the topological variation between the support area and the array area to a minimum characteristic size less than 10 times. The virtual structure can be spaced from each other to a minimum characteristic size of about 1 to about 20 by special technology. This conductive structure can float to avoid grounding. The virtual structure can be connected to a common ground

5. Description of the invention (4 or connected to a fixed potential relative to ground. The second height depends on a certain position in the support area. The semiconductor device may further include a plurality of first metal wires in the support area And the second metal wires are arranged in a layer different from the first metal wires, and the second metal wires are arranged substantially perpendicular to the first direction. The conductive structure is preferably designed The adjacent first and second metal wires will not cover the same conductive structure. The first height and the second height of the structure may be substantially equal. The conductive structure may be used to connect different metal layers. This may be used The conductive structure electrically isolates the first conductive layer from the second conductive layer. In order to support regional circuits, the conductive structure can be used to provide interconnections that are substantially flat on the main surface. Dielectric between area and array area-7- This paper size applies to China National Standard (CNS) A4 (210x 297 public love)

A method for flat transitions on layers, the method includes providing a semiconductor device including a substrate, the main surface of which has an array region and a support region 2. The array of the device is formed in the array area $, and includes hidden cells 、, 己. Structure, the first degree of which exceeds the major surface of the substrate. The virtual memory cell structure (including at least a part of the memory cell structure) is formed in the support area and has a second height exceeding the main surface. A dielectric layer is formed on the memory cell structure in the array area and the virtual memory cell structure in the support area, so that the dielectric layer on the upper surface is substantially flat, which reduces crossover. Topology features on the dielectric region of the array region and the support region. In other methods, the memory cell structure may include a stacked capacitor, and the virtual memory cell structure in the support area may include at least a part of the components used by the stacked capacitor. The dielectric layer can gradually change between the array region and the support region through a virtual memory cell structure with a decreasing k-height above the main surface. The method may further include the step of providing a space between the virtual memory cells in the support area, wherein the space is between about 1 and 20 minimum characteristic sizes by a specific technique. The method may also include the steps of providing a plurality of first metal lines, arranged in a first direction within the support area, and a plurality of second metal lines, arranged in a layer different from the first metal line, The second metal line is substantially perpendicular to the first direction, and the virtual memory cell structure in the support area is designed so that the adjacent first metal line and the second metal line do not cover the same in the support area. Memory cell structure. The first and second heights of the structure may be substantially equal. -8- 494565 A7

These and other objects and detailed examples of the present invention will be read together in detail. The features and advantages are obvious from the following. This specific embodiment needs to be briefly described with reference to the following drawings, in which: This disclosure will present in detail a cross-sectional view of a conductive memory device of a preferred embodiment. 1 is a half-section view of the prior art with topological characteristics; FIG. 2 is a cross-sectional view of a semiconductor device having a reduced topology after a structure is introduced in a support area as in the present invention; and FIG. 3 is a view in the support area as in the present invention. Cross-sectional views of a semiconductor device with a gradually decreasing topology after introducing structures of different heights; FIGS. 4A and 4B are diagrams 5 and 6 illustrating the space of a dielectric layer structure formed on the structure, as described in the present invention, which outlines a conductive structure Threshold to reduce the capacitive coupling between metal lines;% Figure 7 is a cross-sectional view of a semiconductor device as in the prior art, showing the contact connecting different metal layers; Figure 8 is a cross-sectional view of a semiconductor device, showing Adopt the support structure of the present invention to connect the contacts of different metal layers; # FIG. 9 is a cross-sectional view of a semiconductor device, which is used for shielding between different metal layers as described in the present invention. Series junction region into the support. 10A to 10B are cross-sectional views of other semiconductor device structures, illustrating contacts used to connect different metal layers, by using the support formed by the present invention

A7 B7 area structure to reduce metal structure impedance. Detailed description of the specific embodiment of the silk A. The present invention includes forming an array area structure within the area of the support area, so as to reduce the change of the topological characteristics between the second area. The present invention proposes a number of methods to reduce the topology by forming structures, for example, when the memory array includes a stack capacitor structure, a lower electrode template and / or a larger electrode template are provided in the support area. These prototypes may be virtual in shape and have no further work flb, or they may be integrated into the support circuit and operated together with the support circuit. A preferred embodiment of the present invention will now be described with reference to the drawings and from the perspective of a stacked capacitor semiconductor memory structure. With particular reference now to the drawings, the same reference numerals represent similar or identical elements in many points of view, and starting from FIG. 2, a semiconductor device 100 is illustrated. The device 100 includes an array area 102 and a support area 104. Array area 102 includes memory cells including access transistors (not shown) and stacked capacitors 106. The lower electrode 11 of the stacked capacitor 106 is connected to the access circuit. The bit line 105 is formed at the same time as the first metal layer 108. The stacked capacitor device 106 includes a lower electrode 110, a dielectric medium 112, and an upper electrode 114. During the formation of the stacked capacitor 106, all or some of the components of the stacked capacitor 106 are also modeled in the support area 104. As shown in FIG. 2, a lower electrode 11 and a dielectric medium n 2 are formed in the support region 104 to form a dummy structure 119. Advantageously, as in the present invention, after the lower electrode 110 and the edge plate of the dielectric medium U2 are introduced into the support-aid region 04, it is convenient to form a dielectric layer with reduced topology on the device 100. In a preferred embodiment, the topology is reduced by about 10 times the minimum feature size.

Pretend

V. Description of the invention (8) The template of the lower electrode 11o is formed in the support area 104, so that the C1 contact formed in the channel 120 will not be affected by the layout of the template of the lower electrode in a later step. The higher surface 122 of the dielectric layer 118 is significantly flatter than the prior art topology of FIG. 1 in FIG. 1. If these templates are virtual templates without any functionality in the circuit, their size and arrangement can be optimized. A specific device design. It should be understood that although the lower electrode template is used to reduce the topology, in addition to the lower electrode template, its i ... structure can be formed or used as an alternative. For example, it can also be used alone The lower electrode 110, the dielectric medium 112, and / or the upper electrode 114, either in a combined manner in a template of the support area 104 or using a simple dielectric pad. Referring to FIG. 3, as another aspect of the present invention, In addition to filling the entire support area 104 with a lower electrode profile%, the area next to the array area 102 can only be filled by gradually reducing the characteristic south degree in order to fill the support area 104 and the array area. A transition area is formed between 102. Using a lower electrode 110, dielectric 112, and higher electrode 114 structure or stack 130 can form a template next to the array. Next to stack 130 is stack 132, including the lower court. 110 and the dielectric medium 112. Next to the stack 132 is the lower electrode 110 (the higher electrode H4 or any other structure providing a preferred height can also be used). As shown in Figure 3, the topology of the dielectric layer 136 is then Smooth to provide a gradual transition between the array area 102 and the support area 104. When the entire height difference remains substantially the same, a sharp step at the edge of the array is avoided (refer to Figure 1). By providing a gradual decrease in height Structure, a transition area is established between the support area 104 and the array area 102. For the rest of the disclosure here, the structure formed in the support area 104 will be considered as stack 130, stack -11-this paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 494565 A7 -------B7-_ V. Description of the invention (1) " _ " " — Stack 1 3 2 or lower electrode 1 1 0. Referring to Figures 4A and 4B, in the support area The distance between structures formed in 104, for example, the distance between stacks 132 (other structures can also be used), needs to be maintained above a predetermined threshold 地. Graphically, for the distance between stack 132 and stack 132 smaller than the threshold 而, In other words, the surface topology of the dielectric surface 138 following the stack 132 is not consistent (refer to FIG. 4A). In FIG. 4A, the separation distance between the stacks 132 is ten. Di is lower than the threshold 门 dth. The surface 132 of the Π8 is at a height h almost the same as the stack 132. By maintaining the space a below this threshold 値 dth, the density of the stack 132 can be defined next to the array area 102, so that the The density gradually decreases and ends up in the unstacked area. This results in a smooth topology on the surface of the dielectric layer 118. As shown in FIG. 4B, if the separation distance between the stacks 132 is d2, and greater than dth ', a substantially flat surface topology feature will not be formed. ‘Depending on the material of the dielectric layer or other factors, such as the height of the feature. dth can be, '' spoon 1F ', where F is the smallest characteristic size of a particular technology. In a preferred embodiment, t is the smallest characteristic size of a particular technology between about i and about 20. Referring to FIG. 5, the height of the optimized fill-in template geometry and device 'from the density array to the support area is enhanced according to the present invention to enhance the effect of smooth topological changes. Due to the addition of metal features, the geometry and the device that the stack or structure fills the template can optimize the subsequent topology and capacitance effects. The effect of this capacitor is discussed first. In order to minimize the capacitance impact of conductive fill structures on metal level wound capacitors, the structure is best to: 1) Think small as possible (for example, preferably less than about 5 microns); ____________ -1 2-Shicai® Guoxu specifications (21G X 297 male A7

Cover the junction with a metal structure 2) If the density is relatively low when conducting (for example, about 30% of the structure); 3) Float or ground or connect to a fixed potential relative to ground; 4) = as shown in Figure 5 The general device, so that the two adjacent metal line war II. 1) Martin takes a small number of adjacent structures 142, covering, and so on. The structure ⑷ preferably includes a stack 130, a stack 132, and / or a lower electrode 110. In summary, as the structure 142, an electric structure can be used. In this case, the structure 142 is not limited by the electronic criteria as illustrated previously. In summary, the structure 142 may include shapes other than elongated or square. Through the specific threshold 値 in both X and Y directions, the structure H2 is regularly repeated to define the adjacent structure 142 to minimize the coverage. In a preferred embodiment, the angle is about 5. To about 75. Between, and more preferred at about 30. To about 60. So that the pair of metal wires 14 and 〇 have a minimized capacitive coupling between each pair due to the relationship of the conductive structure. Referring to FIG. 6, a schematic structure of a π structure 142 (non-functional) is shown. In order to minimize the topological effect, the shape or structure 142 is preferably: 1) about 2 to 3 times the width of a line of the subsequent metal level; 2) the device as shown in Fig. 6 There is a threshold 间 between the structures 142 in the direction, so that the metal wires are not all covered on the same structure 142 at the same time (that is, so that a single metal wire does not completely cover the same adjacent structure). This is a structure 142 for conducting electricity. -It is possible to adopt structural templates in the support area in a functional way. In the following, several examples of functional structure applications according to the present invention will be described. Referring to FIG. 7, a conventional device 200 is shown, with a capacitor contact 202--13. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 494565 A7 B7-V. Description of the invention ( 11) Connect to the diffusion region 201 of the access transistor 204 in the array region 203. The access transistor 204 includes a gate 206 through which the transistor 204 is enabled to conduct electricity. When conducting, transistor 204 connects bit line 208 and contact 202. The contact 202 is connected to a lower electrode 210 and is capacitively coupled to a common electrode or a higher electrode 212. As shown in FIG. 7, the support region 214 includes a metal layer 216 (preferably, the same metal layer as the bit line 208 is formed). The metal layer 216 may be designated as the layer M0. The metal layer 216 is connected to the higher metal layer 2 1 8 through the contact 219 through the dielectric layer 220 and is also considered a C 1 contact. The higher metal layer may be a M1 layer. The diagram shows the topological features 222 described in the previous art of FIG. Referring to FIG. 8, in addition to filling the support area 300 with a structure 302 (preferably a stack 130) to reduce topology, the present invention includes using a structure 302 template to support the circuit. A structure 302 may be used for conducting the 4 bands, for example, bridging metal lines at other metal levels. At position 301 (illustrated in dashed lines), the structure 302 is connected at some points beyond its length. The contact 304 connects the MO metal line 305 to the structure 302. Structure 302 'is connected to structure 302 and contacts 306. The contact 306 is connected to the metal wire 308 (M1), thus establishing a bridge connecting the wire 305 to the wire 308. Referring to FIG. 9, shielding between the metal layers 320 and 322 can be achieved in the support area 326. The above shielding can be achieved by connecting the lower electrode 324 to a fixed potential (for example, a potential used by a common plate in the array region). Referring to Figs. 10A-B, other connection methods may be made between metal layers in the support area 400. In FIG. 10A, a contact (CC) 402 may be formed on the metal line 404 (M0). Contact (CC) 402 is covered with a lower (or higher) electrode 406 to increase the M0 line 404 (preferably tungsten (W)), CC 402 (preferably polycrystalline, tungsten, tungsten silicide or doped Polycrystalline silicon) and lower electrode 406 (preferably platinum or poly-14)-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

494565 A7 B7 5. Description of the invention (12 silicon) Low conductivity and achieve sufficient conductivity for some wiring applications. This line can be formed in a manner similar to the modified cc contact = described in FIG. 8, but can also be composed of linear features. The contact 40 may be cylindrical. However, strip-shaped contacts 403 can also be used and used with layer 404 for horizontal interconnection. At the same time, it is preferred to use the virtual structure (for example, lower or higher electrode 406) and a combination of contact and metal layers (M0, mb, etc.) of the present invention to manufacture horizontal interconnections (or vertical interconnections). It also covers To support the use of other applications and structures in the support area. For example, in 纟 Tu Gang, 408 is connected to the lower (or higher) electrical 406 through contact 41 (such as' C1 contact). 412 (through bar contact 412 ( For example, q contact) can achieve horizontal inter-installation. The horizontal strip contacts 4G3 and 412 are linear features, while the contacts are in contact with a 10-horse circle. They also cover other architectures and combinations. Reduction of memory device support has been described. The topography of the tart area is -5, and the topology between the E-domain and the array area is illustrated in the two diagrams and is not restrictive). It should be noted that those who are in charge of / can be improved and changed according to the above meaning. Solution ': In the disclosed specific embodiment of the invention, engage in changes in this hairline as outlined in the scope of the attached patent application. The details of the invention have been described and are within the scope of the application for change of profit within the special 1 ^ 奇 # 神 内The knife has been attached to the child Paper Rule Lai Choi®

Claims (1)

1. A semiconductor memory device comprising: an array region and a support region; a 7L structure whose first height exceeds the substrate and whose main surface includes the array region including the main surface of a memory single substrate; the support region includes a virtual structure It is formed therein with a second height exceeding the surface; the Λ J% layer is formed on the memory cell structure in the array region and the virtual structure in the auxiliary region, so that the upper surface of the dielectric layer is consistent on the surface It is flat and can substantially reduce the characteristics of the dielectric layer topology across the array region and the support region. 2. If applying for a semiconductor device in the scope of item i ... the memory unit includes a stacked capacitor, and the virtual structure includes at least-part of the components used by the stacked capacitor. J. The semiconductor device of claim 1 in the scope of the patent, wherein the dummy structure includes at least one of a dielectric material and a conductive material. 4. The semiconductor device as claimed in claim 1, wherein the virtual structure includes at least one of a lower stacked capacitor electrode, a capacitor dielectric, and a higher stacked capacitor electrode. 5. If the semiconductor device according to item 1 of the patent application scope is a virtual structure that gradually decreases in height on the main surface, the dielectric layer may gradually change between the array region and the support region. -'6. The semiconductor device Q1 of the scope of patent application, wherein the virtual structures in the child support area with a specific technology are spaced from each other by about 1 to about 20, which is a small feature size. -16- This paper size applies to the Chinese National Standard (CMS) A4 specification (210 X 297 mm), including the semiconductor device of the first scope of the patent scope of the patent, in which the virtual structure. Pen material 'and the table virtual structure are electrically floating to Avoid grounding. 8. The semiconductor device of claim β, wherein the dummy structure includes a conductive material, and the dummy structure is grounded. 9 · = The semiconductor device according to item 1 of the patent application, wherein the dummy structure includes a conductive material, and the dummy structure is maintained at a fixed potential. 10. The semiconductor device according to item 1 of the scope of patent application, further comprising a plurality of first metal lines arranged in the first direction in the support area; and a plurality of second metal lines arranged in a different direction from the first metal line. Within the layer, the second metal line is substantially perpendicular to the first direction; the Sun virtual structure is designed so that the adjacent first metal line and the adjacent first metal line do not cover the same virtual structure. 1L The semiconductor device according to item 1 of the patent application range, wherein the first height and the second height are substantially equal. 12. The semiconductor device according to item 1 of the patent application scope, wherein the second height depends on a position in the support area. 13. A semiconductor memory device includes: a substrate whose main surface includes an array region and a support region; the array region includes a memory cell structure whose first height exceeds the main surface of the substrate; the support region includes A conductive structure is formed therein with a first dimension exceeding the main surface. The conductive structure has been adopted by a supporting circuit in the supporting area; and a dielectric layer is formed in a memory in the array area. Unit structure and this • 17- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) C8 D8, on top of the conductive structure within the area supported by the patent application, so that the upper surface of the dielectric layer is consistent on the surface It is flat and can substantially reduce the characteristics of the dielectric layer topology across the array region and the support region. 14. The semiconductor device of claim 13 in the patent scope, wherein the memory unit includes a stack and capacitor, and the conductive structure includes at least a part of components used in the stacked capacitor. 15. The semiconductor device according to item 13 of the patent application scope, wherein the conductive structure includes one of a lower stacking capacitor valley electrode and a higher stacking capacitor electrode. " ° 16. If applied ~ The semiconductor device according to item 13 of the patent application, the dielectric layer can gradually change between the array region and the support region through a conductive structure having a gradual decrease in degree on the main surface. 17. The semiconductor device according to item 13 of the patent application scope, wherein the conductive structure is separated from each other in the support area by a specific technology to a minimum characteristic size of about 1 to about 20. 1. The semiconductor device according to claim 13 in which the conductive structure is electrically floating to avoid grounding. 19. The semiconductor device of claim 13 in which the conductive structure is grounded. 20. The semiconductor device of claim 13, wherein the conductive structure is maintained at a fixed potential. -21. The semiconductor device according to item 13 of the scope of patent application, wherein the second height depends on the position in the support area. 22 · If the semiconductor device under the scope of application for item 13 of the patent, further includes a plurality of -18- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ ------- ABCD applied for a range of first metal wires arranged in the first direction within the support area; and a plurality of second metal wires arranged in a layer different from the first metal wire, The second metal line is substantially perpendicular to the first direction; the conductive structure is designed so that the adjacent first metal line and the adjacent second metal line do not cover the same conductive structure. 23. The semiconductor device according to claim 13 in which the first height and the second height are substantially equal. 24. The semiconductor device of claim 3, wherein the conductive structure is used to connect different metal layers. 25. The semiconductor device as claimed in claim 13 in which the conductive structure is used to electronically separate the first conductive layer from the second conductive layer. 26. The semiconductor device of claim 13 in the scope of patent application, in which the conductive structure is employed in order to support a regional circuit 'to provide an interconnection substantially parallel to the main surface. 27 · A method for maintaining a substantially flat transition of a dielectric layer between a support region and an array region on a semiconductor wafer, including the following steps: > providing a semiconductor memory device including a substrate having an array region on a main surface thereof And a support area; forming a device array in the array area, including a memory cell structure 'its first height exceeds the main surface of the substrate;' forming a virtual memory cell structure in the support area, having The second height; and a dielectric layer is formed on the memory cell structure in the array area and the virtual memory cell structure in the support area, so that the dielectric layer's -19- CNS) A4 specification (210 X 297 mm) The upper surface is essentially flat, which can substantially reduce the characteristics of the dielectric layer topology across the array field and the support area. 28. The method according to claim 27 of the patent application, wherein the memory cell structure includes stacked capacitors, and the virtual memory cell structure in the support area includes at least a part of the structure used by the stacked capacitors. element. 29. The method according to item 27 of the patent application, wherein the dielectric layer between the array region and the support region is gradually changed by gradually decreasing the height of the memory cell structure exceeding the main surface. 30. The method of claim 27 of patent scope, further comprising the steps of: providing a space between the memory cell structures in the support area with a specific technology, wherein the space is located at about 1 to about 20 minimum characteristic size between. 3 1. The method according to item 27 of the patent application scope, further comprising the steps of: providing a plurality of first metal wires arranged in the first direction in the support area; and a plurality of second metal wires arranged in the In different layers of the first metal line, the second metal line is substantially perpendicular to the first direction; and the virtual memory cell structure in the support area is designed to enable adjacent first metal lines and adjacent The second metal wire does not cover the same memory cell structure in the gas support area. 32. The method of claim 27, wherein the first height and the second dimension are substantially equal. -20- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)