KR970072066A - 보다 얕은 접합을 이루기 위하여 도펀트 주입에 앞서 사용되는 서브-비정질화 드레시홀드량 주입 에너지를 최적화하는 방법 - Google Patents

보다 얕은 접합을 이루기 위하여 도펀트 주입에 앞서 사용되는 서브-비정질화 드레시홀드량 주입 에너지를 최적화하는 방법 Download PDF

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KR970072066A
KR970072066A KR1019970015965A KR19970015965A KR970072066A KR 970072066 A KR970072066 A KR 970072066A KR 1019970015965 A KR1019970015965 A KR 1019970015965A KR 19970015965 A KR19970015965 A KR 19970015965A KR 970072066 A KR970072066 A KR 970072066A
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dopant
substrate
implantation
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amorphous
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아키프 술탄
리챠드 스콧 리스트
빈센트 모리스 맥닐
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윌리엄 비. 켐플러
텍사스 인스트루먼츠 인코포레이티드
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Abstract

도핑 영역의 도펀트 프로필을 조정하는 방법을 제공한다. 도펀트 주입에 앞서 실리콘 또는 게르마늄과 같은 비 전기적 활성 물질의 서브-비정질화 주입이 수행된다. 비정질화 주입 에너지는 원하는 도펀트 프로필을 달성하도록 최적화된다. 예를 들어, 보다 낮은 에너지는 완만한 접합을 발생시키는 반면, 보다 높은 에너지는 보다 얇은 접합 영역을 발생하도록 사용될 수 있다. 본 발명의 일 실시예에서, MOSFET의 드레인 연장 영역은 붕소 주입에 앞서 실리콘 또는 게르마늄의 서브-비정질화 주입을 사용하여 형성된다. 서브-비정질화 주입 에너지는, 서브-비정질화 주입의 투사 범위가 비정질 실리콘의 붕소 주입의 비소-주입 접합 깊이의 세배보다 크게 선택된다. 이로써 격자간 원소를 접합 영역으로부터 멀리 떨어지게 하여 TED를 감소시킨다.

Description

보다 얕은 접합을 이루기 위하여 도펀트 주입에 앞서 사용되는 서브-비정질화 드레시 홀드량 주입 에너지를 최적화하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 MOSFET의 단면도.

Claims (14)

  1. 기판에 도핑 영역을 형성하는 방법에 있어서; 상기 기판에 서브-비정질화 레벨로 제1투사 범위까지 비전기적 활성 물질을 주입하는 단계; 및 상기 기판에 도펀트를 주입하고 상기 기판을 어닐 처리하여 소정의 접합 깊이(xj)를 형성하는 단계를 포함하는 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  2. 제1항에 있어서, 상기 제1투사 범위는 상기 접합 깊이(xj)보다 커서, 얕고 가파른 접합을 형성하는 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  3. 제1항에 있어서, 상기 제1투사 범위는 상기 접합 깊이(xj)보다 작아서, 깊고 완만한 접합을 형성하는 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  4. 제1항에 있어서, 상기 비 전기적 활성 물질은 주기율표상의 4족 원소인 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  5. 제1항에 있어서, 상기 비 전기적 활성 물질은 실리콘인 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  6. 제1항에 있어서, 상기 비 전기적 활성 물질은 게르마늄인 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  7. 제1항에 있어서, 상기 도펀트는 붕소인 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  8. 제1항에 있어서, 상기 도핑 영역은 얕은 영역이며, 상기 비 전기적 활성 물질 주입 단계는 도펀트 양, 도펀트 에너지 및 스크린 산화막 두께에 의하여 좌우되는 에너지에서 수행되는 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  9. 제1항에 있어서, 상기 도펀트는 BF2 +인 것을 특징으로 하는 기판에 도핑 영역을 형성하는 방법.
  10. 기판에 MOSFET 트랜지스터의 얕은 드레인 연장 영역을 형성하는 방법에 있어서; 모의 비소-주입 접합 깊이보다 세배 정도 큰 제1투사 범위까지 서브-비정질화 레벨로 상기 기판의 영역에 주기율표의 4족으로부터 선택된 물질을 주입하는 단계; 상기 모의 비소-주입 접합 깊이에 개략적으로 대응하는 소정량 및 소정 에너지로 상기 기판의 상기 영역에 도펀트를 주입하는 단계; 및 상기 기판을 어닐 처리하여 상기 도펀트를 확산시키는 단계를 포함하는 것을 특징으로 하는 기판에 MOSFET 트랜지스터의 얕은 드레인 연장 영역을 형성하는 방법.
  11. 제10항에 있어서, 상기 도펀트는 상기 제1투사 범위보다 작은 접합 깊이까지 확산되는 것을 특징으로 하는 기판에 MOSFET 트랜지스터의 얕은 드레인 연장 영역을 형성하는 방법.
  12. 제10항에 있어서, 상기 물질은 실리콘인 것을 특징으로 하는 기판에 MOSFET 트랜지스터의 얕은 드레인 연장 영역을 형성하는 방법.
  13. 제10항에 있어서, 상기 물질은 게르마늄인 것을 특징으로 하는 기판에 MOSFET 트랜지스터의 얕은 드레인 연장 영역을 형성하는 방법.
  14. 제10항에 있어서, 상기 도펀트는 붕소인 것을 특징으로 하는 기판에 MOSFET 트랜지스터의 얕은 드레인 연장 영역을 형성하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970015965A 1996-04-29 1997-04-28 보다 얕은 접합을 이루기 위하여 도펀트 주입에 앞서 사용되는 서브-비정질화 드레시홀드량 주입 에너지를 최적화하는 방법 KR970072066A (ko)

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KR100527207B1 (ko) * 1996-05-08 2005-11-09 어드밴스드 마이크로 디바이시즈, 인코포레이티드 도펀트 확산을 가로막도록 생성된 격자간 변화도를 이용한접합 깊이 및 채널 길이의 제어
US6136673A (en) * 1998-02-12 2000-10-24 Lucent Technologies Inc. Process utilizing selective TED effect when forming devices with shallow junctions
US5970353A (en) * 1998-03-30 1999-10-19 Advanced Micro Devices, Inc. Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6475885B1 (en) * 2001-06-29 2002-11-05 Advanced Micro Devices, Inc. Source/drain formation with sub-amorphizing implantation
GB0200879D0 (en) * 2002-01-16 2002-03-06 Univ Surrey Ion implanted junctions in silicon wafers

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WO1985000694A1 (en) * 1983-07-25 1985-02-14 American Telephone & Telegraph Company Shallow-junction semiconductor devices
FR2578096A1 (fr) * 1985-02-28 1986-08-29 Bull Sa Procede de fabrication d'un transistor mos et dispositif a circuits integres en resultant
JP2773957B2 (ja) * 1989-09-08 1998-07-09 富士通株式会社 半導体装置の製造方法
US5585286A (en) * 1995-08-31 1996-12-17 Lsi Logic Corporation Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device

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