KR970067948A - p-i-n FET 제작 방법 - Google Patents

p-i-n FET 제작 방법 Download PDF

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Publication number
KR970067948A
KR970067948A KR1019960006520A KR19960006520A KR970067948A KR 970067948 A KR970067948 A KR 970067948A KR 1019960006520 A KR1019960006520 A KR 1019960006520A KR 19960006520 A KR19960006520 A KR 19960006520A KR 970067948 A KR970067948 A KR 970067948A
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KR
South Korea
Prior art keywords
fet
light receiving
receiving element
layer
electronic device
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Application number
KR1019960006520A
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English (en)
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KR100212056B1 (ko
Inventor
김성준
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김광호
삼성전자 주식회사
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Priority to KR1019960006520A priority Critical patent/KR100212056B1/ko
Publication of KR970067948A publication Critical patent/KR970067948A/ko
Application granted granted Critical
Publication of KR100212056B1 publication Critical patent/KR100212056B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10335—Indium phosphide [InP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10337—Indium gallium arsenide [InGaAs]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야
p-i-n FET 제작방법
2. 발명이 해결하려고 하는 기술적 과제
본 발명의 과제는 수신단 제작시 수광소자와 전자소자를 단일칩으로 집적하면서 시스템의 성능향상, 생산원가의 절감, 신뢰성 증가 및 집적화에 따르는 기능성의 증가를 이루도록 하는 p-i-n FET 제작 방법을 제공하는데 있다.
3. 발명의 해결방법의 요지
본 발명에서는 p-i-n FET를 제작시, 반 절연성 InP 기판위에 한번의 에피성장을 통해 수광소자와 전자소자 구조를 형성시키는데, 이때 상기 수광소자와 상기 전자소자의 p층을 선택적으로 확산을 통해 형성시킨다.
4. 발명의 중요한 용도
빛을 전기로 바꾸어 주는 수광소자와 전기적 신호를 증폭하는 전자소자

Description

p-i-n FET 제작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 p-i-n FET 구조를 나타낸 단면도.

Claims (7)

  1. 광신호를 전기적 신호로 바꿔주는 광디바이스 수신단에서 p-i-n FET 제작하는 방법에 있어서, 반 절연성 InP 기판위에 한번의 에피성장을 통해 수광소자와 전자소자 구조를 형성시키는 것을 특징으로 하는 p-i-n FET 제작방법.
  2. 제1항에 있어서, 상기 수광소자와 상기 전가소자의 p층을 선택적 확산을 통해 형성시키는 것을 특징으로 하는 p-i-n FET 제작방법.
  3. 제2항에 있어서, 상기 수광소자와 상기 전자소자의 p층을 선택적 확산을 동시에 형성시키는 것을 특징으로 하는 p-i-n FET 제작방법.
  4. 제1항 내지 제3항중 어느 하나의 항에 있어서, 상기 수광소자의 p층과상기 전자소자의 게이트층을 Cd나 Zn으로 확산하는 것을 특징으로 하는 p-i-n FET 제작방법.
  5. 제4항에 있어서, 상기 Cd나 Zn로 확산할 때 열증착기로 확산원을 증착시키는 것을 특징으로 하는 p-i-n FET 제작방법.
  6. 제4항에 있어서, 상기 전자소자에서 기생저항 Rs, Rd등에 영향을 주지않는 정도의 0.15㎛의 채널층을 가지는 것을 특징으로 하는 p-i-n FET 제작방법.
  7. 제6항에 있어서, 상기 전자소자의 채널층의 도핑농도는 전류레벨과 기생저항에 영향을 미치지 않는 8×1016cm-3으로 하는 것을 특징으로 하는 p-i-n FET 제작방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960006520A 1996-03-12 1996-03-12 P-i-n fet 제작 방법 KR100212056B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960006520A KR100212056B1 (ko) 1996-03-12 1996-03-12 P-i-n fet 제작 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960006520A KR100212056B1 (ko) 1996-03-12 1996-03-12 P-i-n fet 제작 방법

Publications (2)

Publication Number Publication Date
KR970067948A true KR970067948A (ko) 1997-10-13
KR100212056B1 KR100212056B1 (ko) 1999-08-02

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ID=19452893

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960006520A KR100212056B1 (ko) 1996-03-12 1996-03-12 P-i-n fet 제작 방법

Country Status (1)

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KR (1) KR100212056B1 (ko)

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Publication number Publication date
KR100212056B1 (ko) 1999-08-02

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