KR970066905A - Data buffering device - Google Patents

Data buffering device Download PDF

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Publication number
KR970066905A
KR970066905A KR1019960006644A KR19960006644A KR970066905A KR 970066905 A KR970066905 A KR 970066905A KR 1019960006644 A KR1019960006644 A KR 1019960006644A KR 19960006644 A KR19960006644 A KR 19960006644A KR 970066905 A KR970066905 A KR 970066905A
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KR
South Korea
Prior art keywords
signal
address
block
storage means
signals
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KR1019960006644A
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Korean (ko)
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KR0183831B1 (en
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김준구
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김광호
삼성전자 주식회사
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Priority to KR1019960006644A priority Critical patent/KR0183831B1/en
Publication of KR970066905A publication Critical patent/KR970066905A/en
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Publication of KR0183831B1 publication Critical patent/KR0183831B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

HDLC/LAPD 콘트롤러에 적용되는 데이터 버퍼링 장치를 공개한다. 그 장치는 데이터 저장을 위한 저장수단과, 제1 및 제2신호에 따라 각각 어드레스 카운팅을 수행하는 제1 및 제2카운터와, 선택신호에 따라 상기 제1 및 제2카운터의 어드레스를 선택 출력하는 멀티플렉서와, 상기 제1 및 제2신호에 따라 어드레스를 카운팅하고, 카운팅된 어드레스를 통해 오버플로 혹은 언더플로가 발생하는 상기 저장수단의 대응되는 메모리 블록의 시작 혹은 마지막 어드레스일 때, 상태신호를 발생되며, 인에이블 신호에 따라 동작 인에이블되는 복수의 블록 제어부, 및 리드/라이트 신호 및 상기 복수의 블록 제어부로부터의 상태신호에 따라, 어드레스 제어를 위해 상기 제1 및 제2신호를 발생하고 인에이블 신호를 발생하여 상기 복수의 블록 제어부에 출력하며 상기 저장수단을 제어하는 제어신호를 발생하는 제어신호 발생부를 구비한 것을 특징으로 한다. 본 발명에 의하면, 보다 빠른 데이터의 송수신이 가능하게 된다.We disclose a data buffering device applied to HDLC / LAPD controller. The apparatus includes storage means for storing data, first and second counters for performing address counting respectively in accordance with the first and second signals, and a selector for selectively outputting the addresses of the first and second counters Counts an address according to the first and second signals and generates a status signal when the counted address is the start or end address of a corresponding memory block of the storage means where overflow or underflow occurs, And generating and outputting the first and second signals for address control in accordance with a read / write signal and a status signal from the plurality of block control units, the plurality of block control units being operable according to an enable signal, A control signal generator for generating a control signal for outputting the signal to the plurality of block controllers and controlling the storage means, And that the feature. According to the present invention, it is possible to transmit and receive data faster.

Description

데이터 버퍼링 장치Data buffering device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 데이터 버퍼링 장치의 바람직한 실시예를 도시한 구성 블록도.FIG. 1 is a block diagram of a data buffering apparatus according to a preferred embodiment of the present invention; FIG.

Claims (3)

데이터 저장을 위한 저장수단; 제1 및 제2신호에 따라 각각 어드레스 카운팅을 수행하는 제1 및 제2카운터; 선택신호에 따라 상기 제1 및 제2카운터의 어드레스를 선택 출력하는 멀티플렉서; 상기 제1 및 제2신호에 따라 어드레스를 카운팅하고, 카운팅된 어드레스를 통해 오버플로 혹은 언더플로가 발생하는 상기 저장수단의 대응되는 메모리 블록의 시작 혹은 마지막 어드레스일 때, 상태신호를 발생되며, 인에이블 신호에 따라 동작 인에이블되는 복수의 블록 제어부; 및 리드/라이트 신호 및 상기 복수의 블록 제어부로부터의 상태신호에 따라, 어드레스 제어를 위해 상기 제1 및 제2신호를 발생하고 인에이블 신호를 발생하여 상기 복수의 블록 제어부에 출력하며 상기 저장수단을 제어하는 제어신호를 발생하는 제어신호 발생부를 구비한 것을 특징으로 하는 데이터 버퍼링 장치.Storage means for storing data; First and second counters respectively performing address counting in accordance with the first and second signals; A multiplexer for selectively outputting addresses of the first and second counters according to a selection signal; Counts the address according to the first and second signals and generates a status signal when the counted address is the start or end address of the corresponding memory block of the storage means where overflow or underflow occurs, A plurality of block controllers operable in accordance with an enable signal; And generates a first signal and a second signal for address control according to a read / write signal and a status signal from the plurality of block control units, generates an enable signal and outputs it to the plurality of block control units, And a control signal generator for generating a control signal for controlling the data buffer. 제1항에 있어서, 상기 저장수단은 하나의 램으로 구성하며, 64바이트의 메모리 용량을 갖는 것을 특징으로 하는 데이터 버퍼링 장치.The data buffering apparatus of claim 1, wherein the storage means comprises one RAM and has a memory capacity of 64 bytes. 제2항에 있어서, 상기 복수의 블록 제어부는 램의 메모리 용량을 4개의 28바이트 메모리 블록 단위로 제어하기 위하여 4개로 구성된 것을 특징으로 하는 데이터 버퍼링 장치.3. The data buffering apparatus of claim 2, wherein the plurality of block controllers comprise four memory units for controlling the memory capacity of the RAM in units of four 28-byte memory blocks. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960006644A 1996-03-13 1996-03-13 Data buffering device KR0183831B1 (en)

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KR0183831B1 KR0183831B1 (en) 1999-05-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100360610B1 (en) * 1998-03-31 2002-11-13 텔레폰아크티에볼라게트 엘엠 에릭슨 Device and method for buffer protection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100360610B1 (en) * 1998-03-31 2002-11-13 텔레폰아크티에볼라게트 엘엠 에릭슨 Device and method for buffer protection

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