KR0133002B1 - Shared memory management and address generating apparatus of flag - Google Patents

Abstract

According to the present invention, when implementing a buffer using shared memory in an ATM switch or a multiplexer, a shared memory management / address generating apparatus using a flag for efficiently managing memory with a small amount of hardware and generating an address for inputting an ATM cell Regarding, the flag management means 21 for managing the memory by controlling the state of the flag as the cell inputs and outputs to the memory; Control means (24) for generating a control signal in accordance with the input / output state of the flag management means (21); Flag storage means (22) for receiving a flag control signal from the flag management means (21) and recording whether a cell is stored in each memory; Memory address generating means 23 which recognizes a free area of the memory according to the state of the flag storing means 22 and selects one of the free areas of the memory to generate a selected memory address and provide it to the flag managing means 21. ; And an address buffering means 25 connected to the memory address generating means 23 for temporarily storing an address where the free area is found.

Description

Shared memory management / address generator by flag

FIG. 1 Buffer Management and Address Generator Applied to ATM Multiplexer

FIG. 2 is a block diagram of shared memory address generation and management using flags.

Figure 3 Flag management function block diagram.

4 is a block diagram of a memory address generation function.

According to the present invention, when implementing a buffer using shared memory in an ATM switch or a multiplexer, a shared memory management / address generating apparatus using a flag for efficiently managing memory with a small amount of hardware and generating an address for inputting an ATM cell It is about.

In general, a cell input from an ATM multiplexer or a switch needs a buffer to temporarily store a cell until it is output by a routing table, and to use the buffer efficiently, a shared rather than using a fixed-length FIFO is required. It is known that implementing a buffer using memory can increase memory utilization efficiency. When shared memory is used to implement a buffer, cells are continuously inputted and outputted in the memory. Therefore, there must be a function of distinguishing and managing the part where the cell is stored and the usable part of the memory area. In order to perform such a memory management function, the FIFO is conventionally used. In case of managing shared memory by using FIFO, in order to initialize FIFO, memory address corresponding to all cell storage areas of memory should be generated and input into FIFO. When a cell is input after initializing the FIFO, the memory address stored in the FIFO is read and used to store the cell. Taking care of it. Such a memory management method can be implemented using a FIFO and a CPU. However, since a FIFO having a size that can store addresses of all memory cell storage areas is used, it requires a lot of hardware and a function for initializing the FIFO. It has a disadvantage such as.

The present invention devised to solve all the problems of the prior art, the flag can be implemented in less hardware than the FIFO by using a flag, the shared memory management / address of the flag so as not to require an initialization process other than a reset The object is to provide a generator.

In order to achieve the above object, the present invention, the flag management means for managing the memory by controlling the state of the flag as the cell input and output to the memory; Control means for generating a control signal in accordance with the input / output state of the flag management means; Flag storage means for receiving a flag control signal from the flag management means and recording whether to store a cell in each memory; Memory address generating means for recognizing a free area of the memory according to the state of the flag storing means, selecting one of the free areas of the memory, generating a selected memory address, and providing the selected memory address to the flag managing means; And an address buffering means for temporarily storing an address which is connected to the memory address generating means and finds an empty area.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a block diagram of an ATM multiplexer to which the present invention is applied. In FIG. 11, an input multiplexer, 12 a shared memory, 13 a memory management and address generator, and 14 an output controller.

The ATM multiplexer shown in the figure shows an example in which a memory management and a memory address generator by flags are applied to an ATM multiplexer.

First, an input multiplexer 11 for multiplexing an ATM cell input into a memory at a subscriber side connection, and the data multiplexed at the input multiplexer 11 is stored in a shared memory 12, wherein the memory management and address generator ( In step 13), a free area of the memory is found and its address is generated, and a flag of the area in which the cell is to be stored is controlled to prevent another cell from being stored until the cell is output. Once the cell is stored in the shared memory 12, the cell is outputted through the network side connection in the output order. At this time, the memory management and address generator 13 controls the flag of the memory area in which the cell is output to control the flag. To control the next inputted cell to use.

2 is a block diagram of a shared memory management and memory address generator according to the present invention, in which 21 is a flag manager, 22 is a flag, 23 is a memory address generator, 24 is a controller, and 25 is an address buffer. Represent each.

In the present invention shown in the figure, the flag management unit 21 for controlling the state of the flag as the cell is input and output to the memory, the flag unit 22 for recording whether or not each memory cell stored, the state of the flag unit 22 The memory address generator 23 recognizes an empty area of the memory and selects one of the free areas of the memory to generate the selected memory address, the controller 24 that generates an appropriate control signal according to the input / output state, and the generated address. It consists of an address buffer 25 for temporary storage.

Each functional unit will be described in detail as follows.

First, the flag manager 21 generates a signal for recording a state change of a corresponding memory area in a flag using a state in which cells are inputted and outputted to a memory and input and output addresses. In order to perform such a function, the flag manager 21 receives an input signal such as a clock and an input / output state from an input / output memory address, an output memory address, and a control function, and operates each flag to control the state of the flag unit 22. Outputs flag control signals such as input values and enable.

The flag unit 22 operates by receiving an input value, an enable signal, a clock, and the like for each unit to record a state of each cell storage unit of the memory, and performs a function of indicating the state of the memory as an output. .

The memory address generator 23 receives the flag output signal of the flag unit 22, finds one of the free areas of the memory, generates an address, and stores the address in the address buffer 25.

In addition, a memory free area address is provided as an input address of the flag manager 21 to be used for memory management.

The controller 24 generates a signal to control the flag manager 21 by receiving an input / output state and a clock when a cell is input / output into a shared memory.

The address buffer 25 temporarily stores the memory address generated by the memory address generator 23. The address buffer 25 adapts the time required to generate the address when the input side continuously requests the memory address. Depth is enough.

3 is an internal configuration diagram of the flag manager 21, in which 31 denotes a state controller and 32 denotes a flag manager.

The flag manager 21 shown in the figure is composed of a state controller 31 which performs a function of controlling the flag manager 32 according to the input / output state, and the flag manager 32 which controls and manages the state of the flag. .

First, the state controller 31 multiplexes the read and write addresses by the control signal and synchronizes the multiplexed address with the timing of the control signal to control the flag manager 32.

The flag manager 32 receives an address and a control signal generated by the state controller 31 and generates a flag control signal to control a corresponding flag, and this signal is changed when a cell input / output occurs in a corresponding memory area. It is used to record this.

4 is an internal configuration diagram of the memory address generator 23, in which 41 denotes a free area searcher and 42 denotes an address generator.

As shown in the drawing, the memory address generator 23 inputs a flag output signal of the flag unit 22 of FIG. 2 to find an empty area in the memory area, and an empty area searcher ( 41 is composed of an address generator 42 which generates an address of an area of memory among the free areas of memory found in 41).

First, the free area detector 41 receives the outputs of the flag unit 22 of FIG. 2 as an input and monitors a free area of the memory, and selects one of these free areas to the address generator 42. to provide.

The address generator 42 receives shared memory free area information selected by the free area searcher 41 and generates a shared memory address for storing a cell. The address generated by the address generator 42 is the second address. It is stored in the address buffer 25 of FIG. This is used to reduce the time required to operate the memory address generation function and the time required for the address. This is used to reduce the time required to operate the memory address generation function and the time required for the address. In order to perform the functions of the blank area searcher 41 and the address generator 42, priority encoding is used in the present invention, and each encoder receives one of eight flag outputs and selects one of the blank areas. It can be extended to the basic unit.

Therefore, the effects of the present invention as described above can be used in various devices using shared memory with a memory address generation and management function composed of a small amount of hardware, and the memory manager of the present invention can resist cells of 512 or less. It is suitable for managing shared memory, and the number of memory used to implement ATM multiplexer and the like is suitable for about 128 cells or less, and it can be used as a device to manage memory used in such a device.

Claims (4)

Flag management means (21) for managing the memory by controlling the state of the flag as the cell inputs and outputs to the memory; Control means (24) for generating a control signal in accordance with the input / output state of the flag management means (21); Flag storage means (22) for receiving a flag control signal from the flag management means (21) and recording whether a cell is stored in each memory; Memory address generating means 23 which recognizes a free area of the memory according to the state of the flag storing means 22 and selects one of the free areas of the memory to generate a selected memory address and provide it to the flag managing means 21. ; And address buffering means (25) connected to said memory address generating means (23) for temporarily storing an address for finding an empty area. 2. The state controller 31 according to claim 1, wherein the flag management means 21 multiplexes cell write and read addresses in accordance with a control signal from the control means 24 and adjusts the timing of the multiplexed address and the control signal. ; And a flag manager (32) for generating a control signal for controlling a flag corresponding to the multiplexed address in said state controller (31). 2. The apparatus of claim 1, wherein the memory address generating means (23) comprises: an empty area finder (41) for receiving an output signal from the flag storing means (22) to find an empty area of a shared memory; An address generator 42 which selects one of the areas found by the empty area searcher 41 and generates an address of the selected area and provides the flag management means 21 and the address buffering means 25 to the flag area; Shared memory management / address generator according to the flag, characterized in that. 4. The shared memory management / address generator according to claim 3, wherein the priority encoding is used to generate a memory address and divided into predetermined flag units so as to find a free area indication of the flag.