KR960025063A - Memory data output control circuit - Google Patents

Memory data output control circuit Download PDF

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Publication number
KR960025063A
KR960025063A KR1019940040187A KR19940040187A KR960025063A KR 960025063 A KR960025063 A KR 960025063A KR 1019940040187 A KR1019940040187 A KR 1019940040187A KR 19940040187 A KR19940040187 A KR 19940040187A KR 960025063 A KR960025063 A KR 960025063A
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KR
South Korea
Prior art keywords
data
dram
data output
system bus
bus
Prior art date
Application number
KR1019940040187A
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Korean (ko)
Inventor
이상남
Original Assignee
구자홍
Lg 전자 주식회사
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Publication date
Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Priority to KR1019940040187A priority Critical patent/KR960025063A/en
Publication of KR960025063A publication Critical patent/KR960025063A/en

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Abstract

종래의 메모리 데이타 출력제어회로는 디램 데이타가 P 점에 곧바로 도착되기 때문에 시스템 버스가 현재 사용중이면 디램에 접근하는 다른 요구들은 데이타가 시스템 버스로 구동되기 전에는 계속 기다리는 상태에 있기 때문에 시스템 성능을 저하시키는 문제점이 있었다.In the conventional memory data output control circuit, since the DRAM data arrives directly at the P point, if the system bus is currently in use, other requests to access the DRAM are kept waiting before the data is driven to the system bus. There was a problem.

따라서 본 발명은 여러장의 프로세서 보드, 메모리 보드가 하나의 시스템 버스를 공유하는 컴퓨터 시스템은 시스템 버스의 사용률이 높을 수록 성능이 저하되는데 이를 방지하기 위하여 시스템 버스의 사용상태에 따라 데이타 응답을 제어하기 위하여 메모리 보드에 데이타 출력 큐를 두어 버스가 바쁜(Busy) 상태이면 디램(DRAM)제어기는 데이타를 큐에 순차적으로 저장해 두었다가 버스가 바쁘지 않으면 데이타를 전송하도록 한 것이다.Therefore, in the present invention, a computer system in which multiple processor boards and memory boards share a single system bus is degraded as the utilization rate of the system bus increases, in order to control data response according to the usage state of the system bus. By placing a data output queue on the memory board and the bus busy, the DRAM controller stores the data in a queue sequentially and transfers the data when the bus is busy.

Description

메모리 테이타 출력제어회로Memory data output control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 데이타 출력제어회로의 구성도, 제4도는 제3도의 상태 천이다.3 is a configuration diagram of a data output control circuit according to the present invention, and FIG. 4 is a state transition of FIG.

Claims (1)

디램에 데이타의 저장 및 판독을 제어하는 제어신호를 발생함과 아울러 데이타 출력신호를 제어하는 디램 제어수단과, 상기 디램 제어수단의 데이타 출력 제어신호에 따라 버스 인터페이스 레지스터를 제어함과 아울러 선입선출 메모리수단을 제어하는 데이타 버스 출력 제어수단과, 상기 디램 제어수단의 제어신호에 따라 데이타를 저장 및 판독하는 디램으로부터 출력된 데이타를 선입선출에 의해 일시적으로 저장하고 상기 버스 인터페이스 레지스터를 통해 시스템 버스로 데이타를 출력하는 선입선출 메모리수단으로 구성하여된 것을 특징으로 한 메모리 데이타 출력제어회로.DRAM control means for generating a control signal for controlling the storage and reading of data in the DRAM and controlling a data output signal; controlling a bus interface register according to the data output control signal of the DRAM control means; A data bus output control means for controlling the means, and data output from the DRAM for storing and reading data in accordance with a control signal of the DRAM control means, by means of first-in first-out, temporarily storing the data to the system bus through the bus interface register. And a first-in, first-out memory means for outputting a memory data output control circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040187A 1994-12-30 1994-12-30 Memory data output control circuit KR960025063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040187A KR960025063A (en) 1994-12-30 1994-12-30 Memory data output control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040187A KR960025063A (en) 1994-12-30 1994-12-30 Memory data output control circuit

Publications (1)

Publication Number Publication Date
KR960025063A true KR960025063A (en) 1996-07-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040187A KR960025063A (en) 1994-12-30 1994-12-30 Memory data output control circuit

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KR (1) KR960025063A (en)

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