KR970053979A - 개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법 - Google Patents
개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법 Download PDFInfo
- Publication number
- KR970053979A KR970053979A KR1019960067153A KR19960067153A KR970053979A KR 970053979 A KR970053979 A KR 970053979A KR 1019960067153 A KR1019960067153 A KR 1019960067153A KR 19960067153 A KR19960067153 A KR 19960067153A KR 970053979 A KR970053979 A KR 970053979A
- Authority
- KR
- South Korea
- Prior art keywords
- flash memory
- floating gate
- drain
- source
- electrons
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract 6
- 230000005669 field effect Effects 0.000 claims abstract 3
- 239000012535 impurity Substances 0.000 claims abstract 3
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract 3
- 150000004706 metal oxides Chemical class 0.000 claims abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract 3
- 230000008672 reprogramming Effects 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
본 발명은 다수의 MOSRETS(금속 산화물 반도체 전계 효과 트랜지스터)를 포함하는 플래시 메모리에 관한 것이다. 각 MOSRETS는 제1도전성 기판과 상기 제 1도전성 기판에 반대되는 제2도전성 타입의 불순물로 도핑된 소스 및 드레인을 포함한다. 소스 및 드레인은 기판의 한 주요 표면 상에서 형성된다. 플러팅 게이트는 소스와 드레인 사이의 채널을 통해서 흐르는 전류를 컨트롤(control)하는 방식으로, 제1절연층을 통해 상기 주요 표면상에 놓여진다. 상기 플로팅 게이트는 채널에서 형성된 공핍층(depletion layer)으로부터 전자가 주입되는 영역에서 전자를 보유하도록 높은 저항을 갖고 있다. 제2절연층을 통해 플로팅 게이트 상에 컨트롤 게이트가 제공된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 명세서에서 언급된 종래의 플래시 메모리의 트랜지스터 셀을 도시한 개략적 단면도.
Claims (4)
- 다수의 MOS(금속 산화물 반도체) 전계효과 트랜지스터를 포함하는 플래시 메모리에 있어서, 각각 제1도전성 기판과; 상기 제1도전성 기판에 반대되는 제2도전성 타입의 불순물로 도핑되고, 상기 기판의 한 주요 표면 상에 형성된 소스 및 드레인과 상기 소스와 상기 드레인 사이의 채널을 통해서 흐르는 전류를 컨트롤하는 방식으로 제1절연층을 통해서 상기 주요 표면상에 위치해 있고, 상기 채널에서 형성된 공핍층츠로부터 전자가 주입된 영역에서 전자를 보유하도록 높은 저항을 갖는 플로팅 게이트; 및 제2절연층을 통해서 상기 플로팅게이트 상에 제공되는 컨트롤 게이트를 포함하는 여러개의 MOS(금속 산화물 반도체)전계효과 트랜지스터를 포함하는 플래시 메모리.
- 제1항에 있어서, 플로팅 게이트가 1×1016/㎝ 내지 1×1018/㎝ 정도의 불순물로 도핑된 다 결정 실리콘으로 이루어진 것을 특징으로 하는 플래시 메모리
- 제1항에 있어서, 상기 공핍 영역은 상기 플러팅 게이트 내에 저장된 전자의 양을 변경시키기 위해 프로그래밍 또는 재프로그래밍 동작을 하는 동안 드레인 전압에 의해서 컨트롤되는 폭을 갖는 것을 특징으로 하는 플래시 메모리.
- 제1항에 있어서, 상기 공핍 영역은 상기 드레인으로부터 상기 소스쪽으로 연장되고, 상기 공핍 영역은 상기 플로팅 게이트 내에 저장된 전자의 양을 변경시키기 위해 프로그래밍 또는 재프로그래밍 동작을 하는 동안 드레인 전압에 의해서 컨트롤되는 폭을 갖는 것을 특징으로 하는 플래시 메모리.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7322889A JP2982670B2 (ja) | 1995-12-12 | 1995-12-12 | 不揮発性半導体記憶装置および記憶方法 |
JP95-322889 | 1995-12-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970053979A true KR970053979A (ko) | 1997-07-31 |
KR100260070B1 KR100260070B1 (ko) | 2000-07-01 |
Family
ID=18148756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960067153A KR100260070B1 (ko) | 1995-12-12 | 1996-12-12 | 개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5787036A (ko) |
JP (1) | JP2982670B2 (ko) |
KR (1) | KR100260070B1 (ko) |
Families Citing this family (40)
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IL125604A (en) | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
US6215148B1 (en) | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6348711B1 (en) | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
US6429063B1 (en) | 1999-10-26 | 2002-08-06 | Saifun Semiconductors Ltd. | NROM cell with generally decoupled primary and secondary injection |
US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
US6396741B1 (en) | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US6677805B2 (en) * | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
US7098107B2 (en) | 2001-11-19 | 2006-08-29 | Saifun Semiconductor Ltd. | Protective layer in memory device and method therefor |
US6885585B2 (en) * | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
US6583007B1 (en) | 2001-12-20 | 2003-06-24 | Saifun Semiconductors Ltd. | Reducing secondary injection effects |
US6975536B2 (en) * | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US7190620B2 (en) * | 2002-01-31 | 2007-03-13 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6700818B2 (en) * | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6917544B2 (en) * | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US6826107B2 (en) * | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
US6967896B2 (en) * | 2003-01-30 | 2005-11-22 | Saifun Semiconductors Ltd | Address scramble |
US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
WO2005094178A2 (en) | 2004-04-01 | 2005-10-13 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
US7366025B2 (en) * | 2004-06-10 | 2008-04-29 | Saifun Semiconductors Ltd. | Reduced power programming of non-volatile cells |
US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
US8400841B2 (en) | 2005-06-15 | 2013-03-19 | Spansion Israel Ltd. | Device to program adjacent storage cells of different NROM cells |
US7184313B2 (en) | 2005-06-17 | 2007-02-27 | Saifun Semiconductors Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US7804126B2 (en) | 2005-07-18 | 2010-09-28 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
CN114361242B (zh) * | 2022-03-14 | 2022-06-14 | 芯众享(成都)微电子有限公司 | 一种可调节阈值电压的平面型碳化硅mosfet及其制备方法 |
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JPS5550667A (en) * | 1978-10-09 | 1980-04-12 | Fujitsu Ltd | Method of fabricating double gate mos-type integrated circuit |
JPH02112287A (ja) * | 1988-10-20 | 1990-04-24 | Sharp Corp | 半導体装置 |
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US5416738A (en) * | 1994-05-27 | 1995-05-16 | Alliance Semiconductor Corporation | Single transistor flash EPROM cell and method of operation |
US5511021A (en) * | 1995-02-22 | 1996-04-23 | National Semiconductor Corporation | Method for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction |
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1995
- 1995-12-12 JP JP7322889A patent/JP2982670B2/ja not_active Expired - Fee Related
-
1996
- 1996-12-12 KR KR1019960067153A patent/KR100260070B1/ko not_active IP Right Cessation
- 1996-12-12 US US08/764,362 patent/US5787036A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5787036A (en) | 1998-07-28 |
KR100260070B1 (ko) | 2000-07-01 |
JPH09162314A (ja) | 1997-06-20 |
JP2982670B2 (ja) | 1999-11-29 |
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