KR970053979A - 개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법 - Google Patents

개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법 Download PDF

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KR970053979A
KR970053979A KR1019960067153A KR19960067153A KR970053979A KR 970053979 A KR970053979 A KR 970053979A KR 1019960067153 A KR1019960067153 A KR 1019960067153A KR 19960067153 A KR19960067153 A KR 19960067153A KR 970053979 A KR970053979 A KR 970053979A
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flash memory
floating gate
drain
source
electrons
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KR1019960067153A
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KR100260070B1 (ko
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다케시 오카자와
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가네꼬 히사시
닛폰 덴키 가부시키가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 다수의 MOSRETS(금속 산화물 반도체 전계 효과 트랜지스터)를 포함하는 플래시 메모리에 관한 것이다. 각 MOSRETS는 제1도전성 기판과 상기 제 1도전성 기판에 반대되는 제2도전성 타입의 불순물로 도핑된 소스 및 드레인을 포함한다. 소스 및 드레인은 기판의 한 주요 표면 상에서 형성된다. 플러팅 게이트는 소스와 드레인 사이의 채널을 통해서 흐르는 전류를 컨트롤(control)하는 방식으로, 제1절연층을 통해 상기 주요 표면상에 놓여진다. 상기 플로팅 게이트는 채널에서 형성된 공핍층(depletion layer)으로부터 전자가 주입되는 영역에서 전자를 보유하도록 높은 저항을 갖고 있다. 제2절연층을 통해 플로팅 게이트 상에 컨트롤 게이트가 제공된다.

Description

개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 명세서에서 언급된 종래의 플래시 메모리의 트랜지스터 셀을 도시한 개략적 단면도.

Claims (4)

  1. 다수의 MOS(금속 산화물 반도체) 전계효과 트랜지스터를 포함하는 플래시 메모리에 있어서, 각각 제1도전성 기판과; 상기 제1도전성 기판에 반대되는 제2도전성 타입의 불순물로 도핑되고, 상기 기판의 한 주요 표면 상에 형성된 소스 및 드레인과 상기 소스와 상기 드레인 사이의 채널을 통해서 흐르는 전류를 컨트롤하는 방식으로 제1절연층을 통해서 상기 주요 표면상에 위치해 있고, 상기 채널에서 형성된 공핍층츠로부터 전자가 주입된 영역에서 전자를 보유하도록 높은 저항을 갖는 플로팅 게이트; 및 제2절연층을 통해서 상기 플로팅게이트 상에 제공되는 컨트롤 게이트를 포함하는 여러개의 MOS(금속 산화물 반도체)전계효과 트랜지스터를 포함하는 플래시 메모리.
  2. 제1항에 있어서, 플로팅 게이트가 1×1016/㎝ 내지 1×1018/㎝ 정도의 불순물로 도핑된 다 결정 실리콘으로 이루어진 것을 특징으로 하는 플래시 메모리
  3. 제1항에 있어서, 상기 공핍 영역은 상기 플러팅 게이트 내에 저장된 전자의 양을 변경시키기 위해 프로그래밍 또는 재프로그래밍 동작을 하는 동안 드레인 전압에 의해서 컨트롤되는 폭을 갖는 것을 특징으로 하는 플래시 메모리.
  4. 제1항에 있어서, 상기 공핍 영역은 상기 드레인으로부터 상기 소스쪽으로 연장되고, 상기 공핍 영역은 상기 플로팅 게이트 내에 저장된 전자의 양을 변경시키기 위해 프로그래밍 또는 재프로그래밍 동작을 하는 동안 드레인 전압에 의해서 컨트롤되는 폭을 갖는 것을 특징으로 하는 플래시 메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960067153A 1995-12-12 1996-12-12 개선된 트랜지스터 셀을 포함하는 플래시 메모리 및 그 메모리를 프로그래밍하는 방법 KR100260070B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7322889A JP2982670B2 (ja) 1995-12-12 1995-12-12 不揮発性半導体記憶装置および記憶方法
JP95-322889 1995-12-12

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KR100260070B1 KR100260070B1 (ko) 2000-07-01

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US5787036A (en) 1998-07-28
KR100260070B1 (ko) 2000-07-01
JPH09162314A (ja) 1997-06-20
JP2982670B2 (ja) 1999-11-29

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