KR970052517A - 인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법 - Google Patents

인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법 Download PDF

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Publication number
KR970052517A
KR970052517A KR1019950069722A KR19950069722A KR970052517A KR 970052517 A KR970052517 A KR 970052517A KR 1019950069722 A KR1019950069722 A KR 1019950069722A KR 19950069722 A KR19950069722 A KR 19950069722A KR 970052517 A KR970052517 A KR 970052517A
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KR
South Korea
Prior art keywords
contact hole
profile
improving
psg layer
thickness
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KR1019950069722A
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English (en)
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KR0170270B1 (ko
Inventor
권혁경
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950069722A priority Critical patent/KR0170270B1/ko
Priority to JP8354622A priority patent/JPH09199585A/ja
Priority to US08/772,431 priority patent/US5912185A/en
Publication of KR970052517A publication Critical patent/KR970052517A/ko
Application granted granted Critical
Publication of KR0170270B1 publication Critical patent/KR0170270B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

인규산화유리층에 형성된 콘택트 홀의 프로파일을 개선하는 방법이 개시된다.
본 발명에 따른 콘택트 홀의 프로파일 개선 방법은 PSG층에 형성된 콘택트 홀의 프로파일을 개선하는 방법에 있어서, PSG층을 그에 형성될 콘택트 홀의 두께보다 높게 증착하는 과정; 상기 증착 과정을 통하여 증착된 PSG층을 리플로우 처리하는 과정: 상기 리플로우 과정을 통하여 리플로우된 PSG층을 콘택트 홀의 두께만큼만 남기고 박리하는 과정; 및 상기 박리 과정의 결과물 상에 콘택트 홀을 형성하는 과정을 포함함을 특징으로 한다.
본 발명에 따른 프로파일 개선 방법은 PSG층을 콘택트 홀이 형성될 두께보다 높게 형성하고 이를 리플로우 처리 후에 제거시킴으로써 PSG층에 형성되는 콘택트 홀의 프로파일을 개선하는 효과를 갖는다.

Description

인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2c도는 본 발명에 따른 프로파일 개선 방법의 흐름을 보이는 공정 단면도이다.

Claims (1)

  1. PSG층에 형성된 콘택트 홀의 프로파일을 개선하는 방법에 있어서, PSG층을 그에,형성될 콘택트 홀의 두께보다 높게 증착하는 과정: 상기 증착 과정을 통하여 증착된 PSG층을 리플로우 처리하는 과정; 상기 리플로우 과정을 통하여 리플로우된 PSG층을 콘택트 홀의 두께만큼만 남기고 박리하는 과정 : 및 상기 박리 과정의 결과물 상에 콘택트 홀을 형성하는 과정을 포함하는 프로파일 개선 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950069722A 1995-12-30 1995-12-30 인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법 KR0170270B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950069722A KR0170270B1 (ko) 1995-12-30 1995-12-30 인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법
JP8354622A JPH09199585A (ja) 1995-12-30 1996-12-20 燐珪酸ガラス層におけるコンタクトホール形成方法
US08/772,431 US5912185A (en) 1995-12-30 1996-12-24 Methods for forming contact holes having improved sidewall profiles

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069722A KR0170270B1 (ko) 1995-12-30 1995-12-30 인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법

Publications (2)

Publication Number Publication Date
KR970052517A true KR970052517A (ko) 1997-07-29
KR0170270B1 KR0170270B1 (ko) 1999-03-30

Family

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KR1019950069722A KR0170270B1 (ko) 1995-12-30 1995-12-30 인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법

Country Status (3)

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US (1) US5912185A (ko)
JP (1) JPH09199585A (ko)
KR (1) KR0170270B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046113A (en) * 1996-10-31 2000-04-04 Texas Instruments Incorporated Combined dry and wet etch for improved silicide formation
US6277757B1 (en) * 1999-06-01 2001-08-21 Winbond Electronics Corp. Methods to modify wet by dry etched via profile
GB2378314B (en) * 2001-03-24 2003-08-20 Esm Ltd Process for forming uniform multiple contact holes
KR100763701B1 (ko) * 2006-08-31 2007-10-04 동부일렉트로닉스 주식회사 컨택트 홀 등방성 프로파일의 형성 방법
KR100755114B1 (ko) * 2006-08-31 2007-09-04 동부일렉트로닉스 주식회사 콘택홀의 형성 방법

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US4176003A (en) * 1978-02-22 1979-11-27 Ncr Corporation Method for enhancing the adhesion of photoresist to polysilicon
US4455568A (en) * 1981-08-27 1984-06-19 American Microsystems, Inc. Insulation process for integrated circuits
DD280633A1 (de) * 1989-03-16 1990-07-11 Werk Fernsehelektronik Veb Verfahren zur herstellung von aetzstrukturen in isolatorschichten auf halbleiterbauelementen
JP2804543B2 (ja) * 1989-10-23 1998-09-30 宮崎沖電気株式会社 半導体素子の製造方法
JPH03283636A (ja) * 1990-03-30 1991-12-13 Nippon Soken Inc 半導体基板の製造方法
JP2519819B2 (ja) * 1990-05-09 1996-07-31 株式会社東芝 コンタクトホ―ルの形成方法
JP3128811B2 (ja) * 1990-08-07 2001-01-29 セイコーエプソン株式会社 半導体装置の製造方法
US5219791A (en) * 1991-06-07 1993-06-15 Intel Corporation TEOS intermetal dielectric preclean for VIA formation
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Publication number Publication date
US5912185A (en) 1999-06-15
KR0170270B1 (ko) 1999-03-30
JPH09199585A (ja) 1997-07-31

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