DE60206012D1 - Verfahren zur Herstellung einer T-förmigen Elektrode - Google Patents

Verfahren zur Herstellung einer T-förmigen Elektrode

Info

Publication number
DE60206012D1
DE60206012D1 DE60206012T DE60206012T DE60206012D1 DE 60206012 D1 DE60206012 D1 DE 60206012D1 DE 60206012 T DE60206012 T DE 60206012T DE 60206012 T DE60206012 T DE 60206012T DE 60206012 D1 DE60206012 D1 DE 60206012D1
Authority
DE
Germany
Prior art keywords
lacquer
formed body
making
metal
shaped electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60206012T
Other languages
English (en)
Other versions
DE60206012T2 (de
Inventor
Dr Maile
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE60206012D1 publication Critical patent/DE60206012D1/de
Publication of DE60206012T2 publication Critical patent/DE60206012T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/945Special, e.g. metal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/951Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electron Beam Exposure (AREA)
  • Battery Electrode And Active Subsutance (AREA)
DE60206012T 2002-02-05 2002-02-05 Verfahren zur Herstellung einer T-förmigen Elektrode Expired - Lifetime DE60206012T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10204621A DE10204621B8 (de) 2002-02-05 2002-02-05 Verfahren zur Herstellung einer mit einem vertikalen Profil versehenen Elektrode und eine derartige Elektrode umfassendes Halbleiterbauelement
EP02001998A EP1335418B1 (de) 2002-02-05 2002-02-05 Verfahren zur Herstellung einer T-förmigen Elektrode

Publications (2)

Publication Number Publication Date
DE60206012D1 true DE60206012D1 (de) 2005-10-13
DE60206012T2 DE60206012T2 (de) 2006-06-22

Family

ID=7713698

Family Applications (2)

Application Number Title Priority Date Filing Date
DE10204621A Expired - Fee Related DE10204621B8 (de) 2002-02-05 2002-02-05 Verfahren zur Herstellung einer mit einem vertikalen Profil versehenen Elektrode und eine derartige Elektrode umfassendes Halbleiterbauelement
DE60206012T Expired - Lifetime DE60206012T2 (de) 2002-02-05 2002-02-05 Verfahren zur Herstellung einer T-förmigen Elektrode

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE10204621A Expired - Fee Related DE10204621B8 (de) 2002-02-05 2002-02-05 Verfahren zur Herstellung einer mit einem vertikalen Profil versehenen Elektrode und eine derartige Elektrode umfassendes Halbleiterbauelement

Country Status (5)

Country Link
US (1) US6881688B2 (de)
EP (1) EP1335418B1 (de)
AT (1) ATE304220T1 (de)
DE (2) DE10204621B8 (de)
TW (1) TWI254992B (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE361550T1 (de) * 2003-05-20 2007-05-15 Koninkl Philips Electronics Nv Struktur einer halbleiter-anordnung und eine methode zur herstellung einer halbleiteranordnung
US7892903B2 (en) * 2004-02-23 2011-02-22 Asml Netherlands B.V. Device manufacturing method and substrate comprising multiple resist layers
DE102005002550B4 (de) * 2005-01-19 2007-02-08 Infineon Technologies Ag Lift-Off-Verfahren
JP4640047B2 (ja) * 2005-08-30 2011-03-02 沖電気工業株式会社 エッチング方法、金属膜構造体の製造方法およびエッチング構造体
KR100795242B1 (ko) * 2006-11-03 2008-01-15 학교법인 포항공과대학교 반도체 소자의 게이트 형성 방법 및 그 게이트 구조
US8158014B2 (en) * 2008-06-16 2012-04-17 International Business Machines Corporation Multi-exposure lithography employing differentially sensitive photoresist layers
US8476168B2 (en) * 2011-01-26 2013-07-02 International Business Machines Corporation Non-conformal hardmask deposition for through silicon etch
JP5768397B2 (ja) * 2011-02-16 2015-08-26 三菱電機株式会社 半導体装置の製造方法
DE102011075888B4 (de) * 2011-05-16 2014-07-10 Robert Bosch Gmbh Halbleitervorrichtung mit mindestens einem Kontakt und Herstellungsverfahren für eine Halbleitervorrichtung mit mindestens einem Kontakt
US9059095B2 (en) 2013-04-22 2015-06-16 International Business Machines Corporation Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
US9548238B2 (en) 2013-08-12 2017-01-17 Globalfoundries Inc. Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same
CN104459854B (zh) * 2013-09-22 2017-12-01 清华大学 金属光栅的制备方法
KR101736270B1 (ko) * 2014-02-14 2017-05-17 한국전자통신연구원 안정화된 게이트 구조를 갖는 반도체 소자 및 그의 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238559A (en) * 1978-08-24 1980-12-09 International Business Machines Corporation Two layer resist system
US4373018A (en) * 1981-06-05 1983-02-08 Bell Telephone Laboratories, Incorporated Multiple exposure microlithography patterning method
US5053348A (en) * 1989-12-01 1991-10-01 Hughes Aircraft Company Fabrication of self-aligned, t-gate hemt
JPH04177738A (ja) * 1990-11-09 1992-06-24 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0590300A (ja) * 1991-09-30 1993-04-09 Fujitsu Ltd 半導体装置の製造方法
JP2723405B2 (ja) * 1991-11-12 1998-03-09 松下電器産業株式会社 微細電極の形成方法
FR2684801B1 (fr) * 1991-12-06 1997-01-24 Picogiga Sa Procede de realisation de composants semiconducteurs, notamment sur gaas ou inp, avec recuperation du substrat par voie chimique.
JPH08172102A (ja) * 1994-12-20 1996-07-02 Murata Mfg Co Ltd 半導体装置の製造方法
JP3591762B2 (ja) * 1998-08-07 2004-11-24 株式会社村田製作所 パターンの形成方法

Also Published As

Publication number Publication date
US6881688B2 (en) 2005-04-19
DE10204621B4 (de) 2009-11-26
DE10204621A1 (de) 2003-08-07
DE60206012T2 (de) 2006-06-22
EP1335418A1 (de) 2003-08-13
TWI254992B (en) 2006-05-11
ATE304220T1 (de) 2005-09-15
EP1335418B1 (de) 2005-09-07
DE10204621B8 (de) 2010-03-25
TW200303056A (en) 2003-08-16
US20030153178A1 (en) 2003-08-14

Similar Documents

Publication Publication Date Title
FR2851181B1 (fr) Procede de revetement d'une surface
DE60206012D1 (de) Verfahren zur Herstellung einer T-förmigen Elektrode
ATE353688T1 (de) Verfahren zur herstellung von elektrodenstrukturen sowie elektrodenstruktur und deren verwendung
ATE394353T1 (de) Verfahren zur herstellung von schichten und schichtsystemen sowie beschichtetes substrat
WO2003060959A3 (en) Method for applying metal features onto barrier layers using electrochemical deposition
AU2002342470A1 (en) Improvements in fluxless brazing
DE60017968D1 (de) Verfahren zur Herstellung von Kohlenstoffnanoröhre
WO2005014892A3 (en) Coating
DE502005008856D1 (de) Zinnbeschichtete Leiterplatten mit geringer Neigung zur Whiskerbildung
ATE511343T1 (de) Verfahren zum herstellen eines formbauteils mit einer integrierten leiterbahn und formbauteil
DE602004015748D1 (de) Lösung zum ätzen von kupferoberflächen und verfahren zur abscheidung von metall auf kupferoberflächen
DE50209164D1 (de) Spritzgegossener Leiterträger und Verfahren zu seiner Herstellung
TW200506107A (en) Multiple-step electrodeposition process for direct copper plating on barrier metals
ATE235795T1 (de) Verfahren, anlage und vorrichtung zur herstellung eines elektrischen verbindungselementes sowie elektrisches verbindungselement und halbzeug
ATE504082T1 (de) Verfahren zur herstellung einer heteroepitaktischen mikrostruktur
WO2002061164A1 (fr) Tole d'acier pretraite et son procede de production
ATE282248T1 (de) Verfahren zum galvanischen bilden von leiterstrukturen aus hochreinem kupfer bei der herstellung von integrierten schaltungen
HK1069607A1 (en) Method for selectively electroplating a strip-shaped, metal support material
EP1398825A3 (de) Substrat und Herstellungsverfahren dafür
DE3860455D1 (de) Verfahren zur herstellung eines keramikbeschichteten metallischen bauteils.
DE502005009420D1 (de) Verfahren zur herstellung einer bereichsweisen metallisierung sowie transferfolie und deren verwendung
DE50310646D1 (de) Verfahren zur beschichtung von metalloberflächen
BR0109887A (pt) Processo de galvonoplastia direta de um substrato plástico, e, substrato plástico
ATE210745T1 (de) Metallischer gegenstand mit einer dünnen mehrphasigen oxidschicht sowie verfahren zu dessen herstellung
DE69929962D1 (de) Verfahren zur herstellung eines verzierten verputzes, mineralischer verputz und werkzeuge zur herstellung des verzierten verputzes

Legal Events

Date Code Title Description
8364 No opposition during term of opposition