KR970030826A - Flash memory device manufacturing method - Google Patents

Flash memory device manufacturing method Download PDF

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Publication number
KR970030826A
KR970030826A KR1019950042779A KR19950042779A KR970030826A KR 970030826 A KR970030826 A KR 970030826A KR 1019950042779 A KR1019950042779 A KR 1019950042779A KR 19950042779 A KR19950042779 A KR 19950042779A KR 970030826 A KR970030826 A KR 970030826A
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KR
South Korea
Prior art keywords
forming
oxide film
layer
nitride
flash memory
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Application number
KR1019950042779A
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Korean (ko)
Other versions
KR0172751B1 (en
Inventor
황준
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019950042779A priority Critical patent/KR0172751B1/en
Publication of KR970030826A publication Critical patent/KR970030826A/en
Application granted granted Critical
Publication of KR0172751B1 publication Critical patent/KR0172751B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 플래쉬 메모리 소자 제조 방법에 관한 것으로, 소자의 높은 항복 전압을 위해 높은 커플링 비(Coupling Ratio)를 가지도록 터널링 영역을 작게 하고 플로팅 게이트 영역을 크게 하는 플래쉬 메모리 제조방법이 개시된다.The present invention relates to a flash memory device manufacturing method, and a flash memory manufacturing method for reducing the tunneling area and the floating gate area to have a high coupling ratio (Coupling Ratio) for the high breakdown voltage of the device is disclosed.

Description

플래쉬 메모리 소자 제조방법Flash memory device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도 내지 제1e도는 본 발명에 따른 플래쉬 메모리 소자 제조 방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

Claims (4)

플래쉬 메모리 소자 제조 방법에 있어서, 제1필드 산화막이 형성된 실리콘 기판상의 선택된 영역에 게이트 산화막, 제1폴리 실리콘층 및 제1질화막을 형성하는 단계와, 상기 전체 구조 상부에 N+이온을 주입하여 소오스 및 드레인 영역을 형성하는 단계와, 상기 전체 구조 상부에 제2질화막을 형성하고 상기 게이트 산화막, 제1폴리실리콘층 및 제1 질화막 측벽에 질화막 스페이서를 형성하는 단계와, 상기 제1필드 산화막 주변에 제2필드 산화막을 형성하고, 상기 제1질화막 및 질화막 스페이서를 제거하는 단계와, 상기 전체 구조 상부에 터널 산화막을 형성하고 상기 제1폴리 실리콘층 측벽에 감광막 스페이서를 형성하는 단계와, 상기 노출된 터널 산화막을 식각 공정으로 식각 한 후, 감광막 스페이서를 제거하는 단계와, 상기 전체 구조 상부에 제2폴리 실리콘층, ONO층 및 제3폴리 실리콘층을 형성하는 단계로 이루어지는 것을 특징으로 하는 플래쉬 메모리 소자 제조방법.A method of manufacturing a flash memory device, comprising: forming a gate oxide film, a first polysilicon layer, and a first nitride film in a selected region on a silicon substrate on which a first field oxide film is formed ; And forming a drain region, forming a second nitride film over the entire structure, and forming a nitride spacer on sidewalls of the gate oxide film, the first polysilicon layer, and the first nitride film, and around the first field oxide film. Forming a second field oxide film, removing the first nitride film and nitride spacers, forming a tunnel oxide film over the entire structure, and forming a photoresist spacer on sidewalls of the first polysilicon layer; After etching the tunnel oxide layer by an etching process, removing the photoresist spacer, and forming a second poly on the entire structure. Forming a silicon layer, an ONO layer and a third polysilicon layer. 제1항에 있어서, 상기 게이트 산화막을 150 내지 200Å의 두께로 증착하는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.2. The method of claim 1, wherein the gate oxide film is deposited to a thickness of 150 to 200 microseconds. 제1항에 있어서, 상기 터널 산화막을 50 내지 100Å의 두께로 성장시키는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.The method of claim 1, wherein the tunnel oxide film is grown to a thickness of 50 to 100 microseconds. 제1항에 있어서, 상기 플로팅 게이트는 제2차 필드 산화막과 오버랩(Overlap)되도록 크게 형성시켜 콘트롤 게이트와 ONO층을 사이에 캐패시턴스가 유지되도록 하는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.The method of claim 1, wherein the floating gate is formed to be largely overlapped with the secondary field oxide layer so that capacitance is maintained between the control gate and the ONO layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950042779A 1995-11-22 1995-11-22 Method of manufacturing flash memory device KR0172751B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950042779A KR0172751B1 (en) 1995-11-22 1995-11-22 Method of manufacturing flash memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950042779A KR0172751B1 (en) 1995-11-22 1995-11-22 Method of manufacturing flash memory device

Publications (2)

Publication Number Publication Date
KR970030826A true KR970030826A (en) 1997-06-26
KR0172751B1 KR0172751B1 (en) 1999-02-01

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Application Number Title Priority Date Filing Date
KR1019950042779A KR0172751B1 (en) 1995-11-22 1995-11-22 Method of manufacturing flash memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470184B1 (en) * 1997-12-10 2005-07-18 주식회사 하이닉스반도체 Flash memory device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470184B1 (en) * 1997-12-10 2005-07-18 주식회사 하이닉스반도체 Flash memory device and its manufacturing method

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KR0172751B1 (en) 1999-02-01

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