KR960006051A - Flash Y pyrom cell and manufacturing method thereof - Google Patents

Flash Y pyrom cell and manufacturing method thereof Download PDF

Info

Publication number
KR960006051A
KR960006051A KR1019940018406A KR19940018406A KR960006051A KR 960006051 A KR960006051 A KR 960006051A KR 1019940018406 A KR1019940018406 A KR 1019940018406A KR 19940018406 A KR19940018406 A KR 19940018406A KR 960006051 A KR960006051 A KR 960006051A
Authority
KR
South Korea
Prior art keywords
oxide film
gate
select gate
cell
floating gate
Prior art date
Application number
KR1019940018406A
Other languages
Korean (ko)
Other versions
KR0135239B1 (en
Inventor
안병진
안재춘
이희열
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940018406A priority Critical patent/KR0135239B1/en
Priority to GB9515216A priority patent/GB2292008A/en
Priority to US08/508,555 priority patent/US5614747A/en
Priority to DE19527682A priority patent/DE19527682B4/en
Priority to CN95115217A priority patent/CN1043097C/en
Publication of KR960006051A publication Critical patent/KR960006051A/en
Application granted granted Critical
Publication of KR0135239B1 publication Critical patent/KR0135239B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 플래쉬 이이피롬 셀(Flash EEPROM Cell) 및 그 제조방법에 관한 것으로, 실렉트 게이트(Select Gate)측벽에 스페이서 형태로 플로팅 게이트(Flating Gate)를 형성하고, 상기 실렉트 게이트와 플로팅 게이트를 감싸도록 컨트롤 게이트(Control Gate)를 형성하여 플래쉬 이이피롬 셀의 과잉소거(Over Erase)및 셀 면적을 감소시킬 수 있는 스플릿 게이트형(Split Gate Type)플래쉬 이이피롬 셀 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EEPROM cell and a method of manufacturing the same. A floating gate is formed in a spacer form on a sidewall of a select gate, and the select gate and the floating gate are formed. The present invention relates to a split gate type flash ypyrom cell capable of forming a control gate to surround and reducing over erase and cell area of the flash ypyrom cell, and a method of manufacturing the same.

Description

플래쉬 이이피롬 셀 및 그 제조방법Flash Y pyrom cell and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4a 내지 3e도는 본 발명에 의한 이이피롬 셀 제조단계를 도시한 소자의 단면도./Figures 4a to 3e is a cross-sectional view of the device showing a step of manufacturing an ypyrom cell according to the present invention.

제4도는 본 발명의 레이아웃도.4 is a layout diagram of the present invention.

제5a 및 5b도는 본 발명의 플래쉬 이이피롬 셀의 동작상태를 설명하기 위한 소자의 단면도.5A and 5B are cross-sectional views of a device for explaining an operating state of a flash easy pyrom cell of the present invention.

Claims (2)

플래쉬 이이피롬 셀에 있어서, P형 기판(11)상에 실렉트 게이트 산화막(18), 실렉트 게이트(20) 및 절연 산화막(22)이 적층구조로 형성되고, 상기 적층구조의 일측벽에 형성되되, 터널 산화막(12)에 의해 상기 기판(11) 및 실렉트 게이트(20)에 전기적으로 절연되는 플로팅 게이트(13)가 형성되며, 상기 플로팅 게이트(13)쪽의 노출된 기판(11)에 드레인 영역(16)이, 상기 실렉트 게이트(20)쪽의 노출기 기판(11)에 소오스 영역(17)이 각각 형성되고, 상기 드레인(16) 및 소오스 영역(17)에 일부 걸쳐지면서 상기 플로팅 게이트(13) 및 실렉트 게이트(20)를 감싸도록 형성되되, 층간 산화막(14)에 의해 상기 드레인, 소오스, 플로팅 게이트 및 실렉트 게이트(16,17,13 및 20) 각각과 전기적으로 절연되는 컨트롤 게이트(15)가 형성된 것을 특징으로 하는 플래쉬 이이피롬셀.In the flash Y pyrom cell, the select gate oxide film 18, the select gate 20, and the insulating oxide film 22 are formed in a stacked structure on the P-type substrate 11, and formed on one side wall of the stacked structure. In addition, the floating gate 13 is electrically insulated from the substrate 11 and the select gate 20 by the tunnel oxide film 12, and the floating gate 13 is formed on the exposed substrate 11 toward the floating gate 13. The drain region 16 has a source region 17 formed on an exposed substrate 11 on the side of the select gate 20, and partially floats over the drain 16 and the source region 17. It is formed to surround the gate 13 and the select gate 20, and is electrically insulated from each of the drain, source, floating gate and the select gate (16, 17, 13 and 20) by the interlayer oxide film (14) Flash easy pyrom cell characterized in that the control gate 15 is formed. 플래쉬 이이피롬 셀 제조방법에 있어서, P형 기판(11)에 필드 산화막(21)을 형성하여 소자 활성영역을 확정한 후 실렉트 게이트 산화막(18)을 성장시키고, 그 상부에 소정의 리소그라피 고정으로 실렉트 게이트(20)와 절연 산화막(22)을 적층구조로 형성하는 단계와, 상기 단계로부터 노출되어 있는 실렉트 게이트 산화막(18)을 제거한 후 전체구조 상부에 터널 산화막(12)을 성장시키고, 그 상부에 폴리실리콘 증착 및 비등방성 식각공정으로 폴리실리콘을 시각하여 실렉트 게이트(20)와 절연 산화막(22) 양측벽쪽에 폴리실리콘 스페이서로 된 플로팅 게이트(13)를 형성하는 단계와, 상기 단계로부터 전체구조 상부에 감광막(23)을 도포한 후 마스크를 이용하여 셀의 드레인 영역을 제외한 부분을 확정하고, 등방성 폴리실리콘 식각 공정으로 소오스 영역쪽에 형성된 플로팅 게이트(13)를 제거하여 드레인 영역쪽의 플로팅 게이트(13)만 남기는 단계와, 상기 단계로부터 감광막(23)을 제거한 후 n형의 고농도 이온주입공정으로 셀의 드레인 및 소오스 영역(16 및 17)을 형성하는 단계와, 상기 단계로부터 전체구조 상부에 층간 산화막(14)을 형성한 후 그 상부에 폴리실리콘 증착 및 소정의 리소그라피공정으로 컨트롤 게이트(15)를 형성하는 단계로 이루어지는 것을 특징으로 하는 플래쉬 이이피롬 셀 제조방법.In the method of manufacturing a flash ypyrom cell, the field oxide film 21 is formed on the P-type substrate 11 to determine the device active region, and then the select gate oxide film 18 is grown, and a predetermined lithography is fixed thereon. Forming the select gate 20 and the insulating oxide film 22 in a stacked structure, removing the select gate oxide film 18 exposed from the step, and then growing the tunnel oxide film 12 over the entire structure, Forming a floating gate 13 made of polysilicon spacers on both sides of the select gate 20 and the insulating oxide film 22 by visually viewing polysilicon by polysilicon deposition and anisotropic etching on the upper portion thereof; After the photoresist film 23 was applied on the entire structure, the portion except the drain region of the cell was determined using a mask and formed on the source region by an isotropic polysilicon etching process. Removing the floating gate 13 to leave only the floating gate 13 on the drain region side, and removing the photoresist film 23 from the step, and then drain and source regions 16 and 17 of the cell by an n-type high concentration ion implantation process. ) And forming an interlayer oxide film 14 on the entire structure from the above step, and then forming the control gate 15 by polysilicon deposition and a predetermined lithography process thereon. Flash Ipyrom cell manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940018406A 1994-07-28 1994-07-28 Flash eeprom cell and its fabrication KR0135239B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019940018406A KR0135239B1 (en) 1994-07-28 1994-07-28 Flash eeprom cell and its fabrication
GB9515216A GB2292008A (en) 1994-07-28 1995-07-25 A split gate type flash eeprom cell
US08/508,555 US5614747A (en) 1994-07-28 1995-07-28 Method for manufacturing a flash EEPROM cell
DE19527682A DE19527682B4 (en) 1994-07-28 1995-07-28 Process for producing an EEPROM flash cell
CN95115217A CN1043097C (en) 1994-07-28 1995-07-28 Method for manufacturing a flash eeprom cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940018406A KR0135239B1 (en) 1994-07-28 1994-07-28 Flash eeprom cell and its fabrication

Publications (2)

Publication Number Publication Date
KR960006051A true KR960006051A (en) 1996-02-23
KR0135239B1 KR0135239B1 (en) 1998-04-22

Family

ID=19389109

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940018406A KR0135239B1 (en) 1994-07-28 1994-07-28 Flash eeprom cell and its fabrication

Country Status (1)

Country Link
KR (1) KR0135239B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100554833B1 (en) * 1999-10-11 2006-02-22 주식회사 하이닉스반도체 Nonvolatile memory device and method for manufacturing the same
KR100575611B1 (en) * 1999-12-22 2006-05-03 매그나칩 반도체 유한회사 Method of fabricating EPROM cell
KR101039244B1 (en) * 2003-07-31 2011-06-08 프리스케일 세미컨덕터, 인크. Nonvolatile memory and method of making same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100554833B1 (en) * 1999-10-11 2006-02-22 주식회사 하이닉스반도체 Nonvolatile memory device and method for manufacturing the same
KR100575611B1 (en) * 1999-12-22 2006-05-03 매그나칩 반도체 유한회사 Method of fabricating EPROM cell
KR101039244B1 (en) * 2003-07-31 2011-06-08 프리스케일 세미컨덕터, 인크. Nonvolatile memory and method of making same

Also Published As

Publication number Publication date
KR0135239B1 (en) 1998-04-22

Similar Documents

Publication Publication Date Title
KR960032761A (en) Semiconductor device, method of manufacturing semiconductor device, split gate type transistor, method of manufacturing split gate type transistor, and nonvolatile semiconductor memory
KR960036040A (en) Ferroelectric memory device and manufacturing method
KR960036088A (en) Flash Y pyrom cell and manufacturing method thereof
KR960026895A (en) Ipyrom cell and preparation method thereof
KR100541047B1 (en) Double-gate MOS transistor and method of fabricating the same
KR960006051A (en) Flash Y pyrom cell and manufacturing method thereof
KR101102966B1 (en) High voltage semiconductor device and method for fabricating the same
KR950007129A (en) Flash memory and its manufacturing method
KR960006050A (en) Flash Y pyrom cell and manufacturing method thereof
KR950011030B1 (en) Making method eeprom
KR960043245A (en) Semiconductor memory device and manufacturing method thereof
KR100444841B1 (en) Flash memory cell fabrication method for forming smoothly floating gate on source/drain region
KR970013338A (en) Nonvolatile Memory Device and Manufacturing Method Thereof
KR0147256B1 (en) Eerpom & method of fabrication
KR970023894A (en) Method of manufacturing thin film transistor
KR970004955B1 (en) Semiconductor memory device and the manufacture method
KR100252925B1 (en) Method of manufacturing flash eeprom in semiconductor device
KR960039406A (en) Manufacturing method of flash Y pyrom cell
KR950012646A (en) Manufacturing method of transistor
KR970024229A (en) Static random access memory device and manufacturing method thereof
KR20010005300A (en) Forming method for non-symmetrical transistor of semiconductor device
KR940022870A (en) Flash Y pyrom and its manufacturing method
KR960009216A (en) Semiconductor device and manufacturing method
KR960039443A (en) Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
KR970004033A (en) Nonvolatile Memory Cells and Manufacturing Method Thereof

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090102

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee