KR100252925B1 - Method of manufacturing flash eeprom in semiconductor device - Google Patents

Method of manufacturing flash eeprom in semiconductor device Download PDF

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KR100252925B1
KR100252925B1 KR1019920018804A KR920018804A KR100252925B1 KR 100252925 B1 KR100252925 B1 KR 100252925B1 KR 1019920018804 A KR1019920018804 A KR 1019920018804A KR 920018804 A KR920018804 A KR 920018804A KR 100252925 B1 KR100252925 B1 KR 100252925B1
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South Korea
Prior art keywords
polysilicon layer
layer
semiconductor device
gate insulating
flash eeprom
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KR1019920018804A
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Korean (ko)
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김남종
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김영환
현대반도체주식회사
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Abstract

PURPOSE: A method of manufacturing a flash EEPROM in a semiconductor device is provided to implement a flash EEPROM having a large scale and high density by minimizing an isolation area. CONSTITUTION: An oxide(2) is formed on a substrate(1), and a gate insulating layer(4), a second polysilicon layer(5), an ONO layer(6) and a third polysilicon layer(7) are sequentially formed on overall structure after patterning a first polysilicon layer(3) on a surface of the oxide(2) except isolation areas between respective cells. Then, the gate insulating layer(4), second polysilicon layer(5), ONO layer(6) and third polysilicon layer(7) on the first polysilicon layer(3) except channel areas of respective cells are removed, and a source/drain(8) is formed by implanting ions.

Description

반도체장치의 플래쉬 이피롬 제조 방법Flash Ipyrom Manufacturing Method Of Semiconductor Device

제1도는 본발명의 플래쉬 이피롬 제조를 설명하기위한 공정 단면도.1 is a cross-sectional view for explaining the production of a flash pyrom of the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 기판 2 : 산화막1 substrate 2 oxide film

3 : 제1 폴리 실리콘층 4 : 게이트 절연막3: first polysilicon layer 4: gate insulating film

5 : 제2 폴리 실리콘층 6 : ONO막5: second polysilicon layer 6: ONO film

7 : 제3 폴리 실리콘층 8 : 소오스/드레인7: third polysilicon layer 8: source / drain

본발명은 반도체장치의 플래쉬 이피롬(Flash EPROM)에 관한 것으로, 특히 대 용량 및 고 밀도(High Density)를 갖는 플래쉬 이피롬을 실현 하기에 적당하도록 한 반도체장치의 플래쉬 이피롬 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EPROM of a semiconductor device, and more particularly, to a method for manufacturing a flash pyrom of a semiconductor device, which is suitable for realizing a flash pyrom having high capacity and high density. .

일반적으로, 이피롬이란 메모리 안에 있는 내용을 지울 수 있고 다시 프로그램을 입력할 수 있는 롬의 일종으로써 지울 때에는 자외선을 쪼여서 지우며 프로그램을 입력할 때에는 롬 라이터(ROM writer)를 사용한다.In general, Epirom is a type of ROM that can erase contents in memory and input a program again. When erasing, it uses a UV writer to erase a program and uses a ROM writer to input a program.

사용 용도로는 시스템 프로그램을 개발하는데, 빠른 회수 시간이 중요한 고성능 마이크로컴퓨터 시스템에 적합하다.Its use is to develop a system program, which is suitable for high performance microcomputer systems where fast payback times are critical.

그러나, 종래의 이피롬은 다음과 같은 결점이 있다.However, the conventional pyromium has the following drawbacks.

첫째, SOI(Silicon On Insulator)구조를 갖으므로 원가가 상승한다.First, the cost rises as it has a silicon on insulator (SOI) structure.

둘째, 게이트 절연막 및 아이솔레이션(Isolation)이 각각 이루어지므로 제조 공정이 복잡해진다.Second, since the gate insulating film and the isolation are respectively formed, the manufacturing process is complicated.

셋째, 아이솔레이션이 차지하는 면적이 크므로 고 밀도의 이피롬을 형성할 수 없다.Third, because of the large area occupied by the isolation, it is not possible to form a high-density epirome.

본발명은 이와같은 종래의 결점을 감안하여 안출한 것으로, 아이솔레이션이 차지하는 면적을 최소화시켜 대 용량 및 고 밀도를 갖는 플래쉬 이피롬을 실현할 수 있는 반도체장치의 플래쉬 이피롬 제조 방법을 제공 하는데 그 목적이 있다.The present invention has been devised in view of the above-mentioned drawbacks, and aims to provide a method for manufacturing a flash epipyrome of a semiconductor device capable of minimizing the area occupied by the isolation to realize a flash pyrom having a high capacity and a high density. have.

이하에서 이와같은 목적을 달성하기 위한 본발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving this purpose will be described in detail by the accompanying drawings.

제1도는 본발명의 공정 단면도로, 제1도(a)와 같이 기판(P형 실리콘)(1)위에 산화막(2)을 형성하고, (b)와 같이 산화막(2)위 각 소자간 절연 영역을 제외한 표면에 제1 폴리 실리콘층(n+형 또는 p+형 폴리 실리콘)(3)을 패터닝(Patterning) 한 후 (c)와같이 전 표면에 게이트 절연막(열 산화막(Rapid Thermal Oxidation))(4), 제2 폴리 실리콘층(n-형 폴리 실리콘)(5), ONO막(산화막, 질화막, 산화막이 차례로 형성된 막)(6), 제3 폴리 실리콘층(7)을 차례로 형성한다.FIG. 1 is a cross-sectional view of the process of the present invention, in which an oxide film 2 is formed on a substrate (P-type silicon) 1 as shown in FIG. 1 (a), and as shown in FIG. After patterning the first polysilicon layer (n + type or p + type polysilicon) 3 on the surface except the region, the gate insulating film (Rapid Thermal Oxidation) on the entire surface as shown in (c). (4), a second polysilicon layer (n - type polysilicon) 5, an ONO film (film formed with an oxide film, a nitride film, and an oxide film) 6, and a third polysilicon layer 7 are formed in this order.

다음, (d)와 같이 각소자의 채널 영역을 제외한 제1 폴리 실리콘층(3) 위쪽의 상기 게이트 절연막(4), 제2 폴리 실리콘층(5), ONO막(6), 제3 폴리 실리콘층(7)을 제거하고, 소오스/드레인 영역에 n+이온을 주입하여 (e)와같이 소오스/드레인(8)을 형성 하므로써 게이트, 활성층, 그리고 소오스/드레인(8)으로 이루어지는 박막트랜지스터(TFT)를 구현한다.Next, as shown in (d), the gate insulating film 4, the second polysilicon layer 5, the ONO film 6, and the third polysilicon above the first polysilicon layer 3 except for the channel region of each device. By removing the layer 7 and implanting n + ions into the source / drain regions to form the source / drain 8 as shown in (e), a thin film transistor (TFT) comprising a gate, an active layer, and a source / drain 8 is formed. ).

이상에서 설명한 바와같이 본발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, SOI구조를 갖으나 이며 만들어진 SIMOX등과 같은 SOI 웨이퍼(Wafer)가 필요하지 않으므로 원가가 절감된다.First, it has an SOI structure and costs are reduced because SOI wafers such as SIMOX are not needed.

둘째, 게이트 절연막(4) 형성시 아이솔레이션이 동시에 이루어지므로 제조공정이 간단해 진다.Second, since isolation is simultaneously performed when the gate insulating film 4 is formed, the manufacturing process is simplified.

셋째, 아이솔레이션 면적이 매우 작아 고 밀도의 이피롬을 실현할 수 있다.Third, the isolation area is very small, and high density pyrom can be realized.

Claims (1)

기판(1)위에 산화막(2)을 형성하고, 산화막(2)위 각 소자간 절연 영역을 제외한 표면에 제1 폴리 실리콘층(3)을 패터닝 한 후 전 표면에 게이트 절연막(4), 제2 폴리 실리콘층(5), ONO막(6), 제3 폴리 실리콘층(7)을 차례로 형성하는 단계와, 각소자의 채널 영역을 제외한 제1 폴리 실리콘층(3) 위쪽의 상기 게이트 절연막(4), 제2 폴리 실리콘층(5), ONO막(6), 제3 폴리 실리콘층(7)을 제거하고, 소오스/드레인 영역에 이온을 주입하여 소오스/드레인(8)을 형성하는 단계를 차례로 실시하여 이루어지는 반도체장치의 이피롬 제조 방법.An oxide film 2 is formed on the substrate 1, the first polysilicon layer 3 is patterned on the surface of the oxide film 2 except for the insulating region between the elements, and then the gate insulating film 4 and the second surface are formed on the entire surface. Forming a polysilicon layer (5), an ONO film (6), and a third polysilicon layer (7) in sequence, and the gate insulating film (4) above the first polysilicon layer (3) excluding the channel region of each device. ), Removing the second polysilicon layer 5, the ONO film 6, and the third polysilicon layer 7, and implanting ions into the source / drain regions to form the source / drain 8. A method for producing epipyrom in a semiconductor device, which is carried out.
KR1019920018804A 1992-10-13 1992-10-13 Method of manufacturing flash eeprom in semiconductor device KR100252925B1 (en)

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KR1019920018804A KR100252925B1 (en) 1992-10-13 1992-10-13 Method of manufacturing flash eeprom in semiconductor device

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