KR0172751B1 - Method of manufacturing flash memory device - Google Patents
Method of manufacturing flash memory device Download PDFInfo
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- KR0172751B1 KR0172751B1 KR1019950042779A KR19950042779A KR0172751B1 KR 0172751 B1 KR0172751 B1 KR 0172751B1 KR 1019950042779 A KR1019950042779 A KR 1019950042779A KR 19950042779 A KR19950042779 A KR 19950042779A KR 0172751 B1 KR0172751 B1 KR 0172751B1
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- Prior art keywords
- oxide film
- forming
- flash memory
- layer
- polysilicon layer
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000008878 coupling Effects 0.000 abstract description 7
- 238000010168 coupling process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract description 7
- 230000005641 tunneling Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 플래쉬 메모리 소자 제조 방법에 관한 것으로, 소자의 높은 항복 전압을 위해 높은 커플링 비(Coupling Ratio)를 가지도록 터널링 영역을 작게 하고 플로팅 게이트 영역을 크게 하는 플래쉬 메모리 제조 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flash memory device, and a method of manufacturing a flash memory for reducing a tunneling region and increasing a floating gate region to have a high coupling ratio for a high breakdown voltage of the device is disclosed.
Description
제1a도 내지 제1e 도는 본 발명에 따른 플래쉬 메모리 소자 제조 방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 제1 필드산화막1 silicon substrate 2 first field oxide film
3 : 게이트 산화막 4 : 제1 폴리실리콘층3: gate oxide film 4: first polysilicon layer
5 : 제1 산화막 6 : 소오스 및 드레인 영역5: first oxide film 6: source and drain regions
7 : 질화막 스페이서 8 : 감광막 스페이서7 nitride film spacer 8 photosensitive film spacer
9 : 터널 산화막 10 : 제2 필드산화막9 tunnel oxide film 10 second field oxide film
11 : 제2 폴리실리콘층 12 : ONO 층11: second polysilicon layer 12: ONO layer
13 : 제3 폴리실리콘층13: third polysilicon layer
본 발명은 플래쉬 메모리 소자 제조 방법에 관한 것으로, 특히 높은 커플링 비(Coupling Ratio)를 갖는 플래쉬 메모리 소자 제조 방법에 관한 것이다.The present invention relates to a flash memory device manufacturing method, and more particularly to a flash memory device manufacturing method having a high coupling ratio (Coupling Ratio).
일반적으로 플래쉬 메모리 소자가 고집적화되고 시스템이 소형 경량화 되고 휴대용화 되면서 EPROM의 장점과 EEPROM의 장점을 지닌 소자가 요구되어 플래쉬 EEPROM(이하, 플래쉬 메모리 소자라함)이 개발되었다. 플래쉬 메모리 소자는 한개의 트랜지스터로서 한 비트의 저장 상태를 실현하며 전기적으로 프로그램과 소거(Erase)를 할 수 있는데, 플래쉬란 소거 동작 동안에 전체 메모리 블록 혹은 일부 메모리 블록이 동시에 소거된다는 것에서 유래 되었다. 플래쉬 메모리 소자의 프로그램과 소거시 12V/5V 겸용(혹은 5V 단일 전원)을 사용하는데, 프로그램은 핫 전자(Hot Electron)를 이용하고, 소거는 F-N(Fowler-Nordheim)터널링을 이용한다. 그러나 플래쉬 메모리 소자가 고집적화되면서 높은 항복 전압이 필요하게 되고, 이에 따라 높은 커플링 비가 요구되지만 종래 기술로는 커플링 비를 높이는데 한계가 있다.In general, as flash memory devices have been highly integrated, and systems have become smaller, lighter, and portable, a device having advantages of EPROM and EEPROM is required, and a flash EEPROM (hereinafter referred to as a flash memory device) has been developed. The flash memory device can be programmed and erased electrically by realizing a bit storage state as one transistor, which is derived from the fact that the entire memory block or some memory blocks are simultaneously erased during the erase operation. When programming and erasing flash memory devices, a 12V / 5V (or 5V single supply) is used. The program uses hot electrons and the erase uses Fowler-Nordheim (F-N) tunneling. However, as the flash memory device is highly integrated, a high breakdown voltage is required. Accordingly, a high coupling ratio is required, but there is a limit in increasing the coupling ratio in the related art.
따라서 본 발명은 높은 커플링 비를 가질 수 있는 플래쉬 메모리 소자 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device that can have a high coupling ratio.
상기한 목적을 달성하기 위한 본 발명은 제1필드산화막이 형성된 실리콘 기판상의 선택된 영역에 게이트 산화막, 제1폴리실리콘층 및 제1질화막을 형성하는 단계와, 상기 전체 구조 상부에 N+이온을 주입하여 소오스 및 드레인 영역을 형성하는 단계와, 상기 전체 구조 상부에 제2질화막을 형성하고 상기 게이트 산화막, 제1필드산화막 주변에 제2필드산화막을 형성하고, 상기 제1질화막 및 질화막 스페이서를 제거하는 단계와, 상기 전체 구조 상부에 터널 산화막을 형성하고 상기 제1폴리실리콘층 측벽에 감광막 스페이서를 형성하는 단계와, 상기 노출된 터널 산화막을 식각공정으로 식각 한후, 감광막 스페이서를 제거하는 단계와, 상기 전체구조 상부에 제2폴리실리콘층, ONO층 및 제3폴리실리콘층을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is formed by forming a gate oxide film, a first polysilicon layer and a first nitride film in a selected region on the silicon substrate on which the first field oxide film is formed, and implanting N + ions on the entire structure Forming source and drain regions, forming a second nitride film over the entire structure, forming a second field oxide film around the gate oxide film and the first field oxide film, and removing the first nitride film and the nitride spacer Forming a tunnel oxide layer over the entire structure and forming a photoresist spacer on sidewalls of the first polysilicon layer, etching the exposed tunnel oxide layer by an etching process, and then removing the photoresist spacer; And forming a second polysilicon layer, an ONO layer, and a third polysilicon layer on the entire structure.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1f도는 본 발명에 따른 플래쉬 메모리 소자 제조 방법을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.
제1a도와 관련하여 , 제1 필드산화막(2)이 형성된 실리콘 기판(1)상에 게이트 산화막(3)이 150내지 200Å의 두께로 증착되고, 제1 폴리실리콘층(4) 및 제1질화막(5)이 형성된다. 상기 실리콘 기판(1)상에 N+이온이 주입되어 소오스 및 드레인 영역(6)이 형성된다. 이후 상기 전체 구조 상부에 열공정이 실시된다.Referring to FIG. 1A, a gate oxide film 3 is deposited to a thickness of 150 to 200 GPa on the silicon substrate 1 on which the first field oxide film 2 is formed, and the first polysilicon layer 4 and the first nitride film ( 5) is formed. N + ions are implanted into the silicon substrate 1 to form source and drain regions 6. Thereafter, a thermal process is performed on the entire structure.
제1b도와 관련하여, 전체 구조 상부에 제2질화막이 증착된후, 전면 식각공정이 실시되어 상기 제1폴리실리콘층 및 제1질화막(4및5)의 측벽에 질화막 스페이서(7)가 형성된다.In relation to FIG. 1B, after the second nitride film is deposited over the entire structure, a front surface etching process is performed to form nitride spacers 7 on sidewalls of the first polysilicon layer and the first nitride films 4 and 5. .
제1c도와 관련하여, 전체 구조 상부에 제2필드산화막(10)이 형성된 후, 상기 질화막 스페이서(7) 및 제1질화막(5)이 제거된다. 전체 구조 상부에 터널 산화막(9)이 50내지 100Å의 두께로 성장되고 감광막이 도포된 후 전면 식각 공정이 실시되어 상기 제1폴리실리콘층(4)의 터널 산화막 측벽에 감광막 스페이서(8)가 형성된다.With reference to FIG. 1C, after the second field oxide film 10 is formed over the entire structure, the nitride spacer 7 and the first nitride film 5 are removed. The tunnel oxide film 9 is grown to a thickness of 50 to 100 에 over the entire structure, and a photoresist film is applied, followed by a front etching process to form a photoresist spacer 8 on the sidewalls of the tunnel oxide film of the first polysilicon layer 4. do.
제1d도와 관련하여, 상기 터널 산화막(9)의 노출된 부분이 식각된 후, 감광막 스페이서(8)가 제거된다.With respect to FIG. 1d, after the exposed portion of the tunnel oxide film 9 is etched, the photoresist spacer 8 is removed.
상기 전체 구조 상부에 폴리실리콘이 증착되어 제2폴리실리콘층(11)이 형성된 후, 식각공정에 의해 패터닝되어 형성된 제2폴리실리콘층(11)에 불순물이 도핑된다. 제2폴리 실리콘층(11) 상부에 ONO층(12)이 형성된다.After the polysilicon is deposited on the entire structure to form the second polysilicon layer 11, impurities are doped into the second polysilicon layer 11 formed by patterning by an etching process. The ONO layer 12 is formed on the second polysilicon layer 11.
따라서, 상기 제1폴리실리콘층(4)과 제2폴리실리콘층(11)이 플로팅 게이트로 작용한다.Thus, the first polysilicon layer 4 and the second polysilicon layer 11 serve as floating gates.
제1e도와 관련하여, 전체 구조 상부에 폴리실리콘이 증착되어 제3폴리실리콘층(13)이 형성되고, 상기 제3폴리실리콘층이(13) 식각공정으로 패터닝되어 콘트롤 게이트가 형성된다.In relation to FIG. 1e, polysilicon is deposited on the entire structure to form a third polysilicon layer 13, and the third polysilicon layer is patterned by an etching process to form a control gate.
상술한 바와 같이 본 발명은 터널링 영역을 작게 하고 플로팅 게이트 영역을 크게 하여 높은 커플링 비를 가질 수 있는 탁월한 효과가 있다.As described above, the present invention has an excellent effect of reducing the tunneling region and increasing the floating gate region to have a high coupling ratio.
본 발명에 의하면 터널영역이 0.2∼0.5mm/side로 미세하게 형성되고, 플로팅 게이트는 필드산화막과 오버랩(Overlap)되도록 크게 형성되므로 콘트롤 게이트의 ONO층 사이에 큰 캐패시턴스가 유지된다.According to the present invention, the tunnel region is finely formed at 0.2 to 0.5 mm / side, and the floating gate is largely formed to overlap with the field oxide film, so that large capacitance is maintained between the ONO layers of the control gate.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042779A KR0172751B1 (en) | 1995-11-22 | 1995-11-22 | Method of manufacturing flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042779A KR0172751B1 (en) | 1995-11-22 | 1995-11-22 | Method of manufacturing flash memory device |
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| Publication Number | Publication Date |
|---|---|
| KR970030826A KR970030826A (en) | 1997-06-26 |
| KR0172751B1 true KR0172751B1 (en) | 1999-02-01 |
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| KR1019950042779A KR0172751B1 (en) | 1995-11-22 | 1995-11-22 | Method of manufacturing flash memory device |
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| KR100470184B1 (en) * | 1997-12-10 | 2005-07-18 | 주식회사 하이닉스반도체 | Flash memory device and its manufacturing method |
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