KR100850065B1 - Method for fabricating a flash memory device - Google Patents

Abstract

A method of manufacturing a flash memory device includes forming a first gate insulating film on a semiconductor substrate, depositing polysilicon on the first gate insulating film, patterning the first polysilicon film so as to round the top edge in an island shape, Forming a second gate insulating film on the semiconductor substrate so as to cover the floating gate, forming a control gate in the longitudinal direction so as to overlap with the floating gate on the second gate insulating film, Forming a source region and a drain region by doping an exposed portion of the semiconductor substrate with an impurity of a conductivity type different from that of the semiconductor substrate using the control gate as a mask; And the floating gate and the control gate And in both sides of a step of forming a select gate, and poly layer. Therefore, it is possible to reduce power consumption while easily programming and erasing data in the floating gate, to prevent shortening of the element lifetime due to field concentration at the upper edge of the floating gate, It is possible to prevent a channel effect (short channel effect) from being generated.

Flash memory, floating gate, field concentration, select gate, FN electron tunneling

Description

[0001] METHOD FOR FABRICATING A FLASH MEMORY DEVICE [0002]

1A and 1B are process drawings showing a method of manufacturing a flash memory device according to the related art.

2A to 2C are process drawings showing a method of manufacturing a flash memory device according to the present invention.

Description of the Related Art [0002]

31: semiconductor substrate 33: first gate insulating film

35: floating gate 36: photoresist pattern

37: second gate insulating film 39: control gate

41: source region 43: drain region

45: insulating film 47: select gate

49: poly layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a NOR type non-volatile flash memory device.

Generally, nonvolatile memories include EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), and flash memory.

EPROM consists of one transistor per cell and has a smaller size and faster operation speed than EEPROM. However, when data is input by using a separate device when programming, the EPROM is used in a system, There is an inconvenience that it is required to emit ultraviolet rays (Ultra-Violet) when the data is erased from the system.

On the other hand, the EEPROM can update data on the system with a single power supply of 5 V, but has two transistors per cell, which are larger in size than EPROM, slow in operation, and expensive.

A flash memory device is developed and produced by combining the characteristics of the EPROM and the EEPROM described above. A flash memory device has one transistor in one cell and is capable of upgrading data on the system. In addition, the principle of EPROM is used for programming, and the principle of EEPROM is used for erasing data. The cell size is small and suitable for large capacity.

Such a flash memory is classified into a NAND type and a NOR type according to the configuration of a cell. The type in which the N-MOS constituting the memory cell is formed by a separate line is called a NOR type , And the type in which the N-MOSs are connected on the same line is referred to as a NAND type.

The NOR flash memory device has the advantages of high random access speed and programmability per byte.

Referring to FIGS. 1A and 1B, a process drawing showing a method of manufacturing a flash memory device according to the prior art is shown.

First, as shown in FIG. 1A, a first gate insulating film 13 used as a tunnel oxide film is formed on a semiconductor substrate 11 by a thermal oxidation method, and then a polycrystalline silicon / RTI > The polycrystalline silicon is patterned by a photolithography method to form an island-shaped floating gate 15.

Next, as shown in FIG. 1B, a second gate insulating film 17 is formed on the semiconductor substrate 11 so as to cover the floating gate 15. In this process, the second gate insulating film 17 is formed to have an ONO (oxide film / nitride film / oxide film) structure.

Then, polycrystalline silicon is deposited on the second gate insulating film 17 and patterned by a photolithography method to form the control gate 19. At this time, the control gate 19 overlaps with the island-shaped floating gate 15 and is formed long in the longitudinal direction.

Source and drain regions 21 and 23 are formed by doping an exposed portion of the semiconductor substrate 11 with a control gate 19 as a mask and doping impurities of a conductivity type different from that of the semiconductor substrate 11. [

However, the conventional flash memory device according to the related art has a problem that not only a large amount of power is consumed, but also overerase occurs when data is deleted, by programming or deleting data in the floating gate by applying voltage to the control gate .

In addition, since the upper edge of the floating gate is formed with a sharp edge, the electric field is concentrated to shorten the lifetime of the device, and as the degree of integration increases, the channel length decreases and a short channel effect is generated.

Therefore, it is an object of the present invention to provide a method of manufacturing a flash memory device capable of reducing data consumption and programming of a floating gate.

It is another object of the present invention to provide a method of manufacturing a flash memory device capable of preventing shortening of device life due to electric field concentration in the upper edge of a floating gate.

It is still another object of the present invention to provide a method of manufacturing a flash memory device capable of preventing a short channel effect due to a decrease in channel length.

According to an aspect of the present invention, there is provided a method of manufacturing a flash memory device, including: forming a first gate insulating film on a semiconductor substrate; depositing polysilicon on the first gate insulating film; Forming a second gate insulating film on the semiconductor substrate so as to cover the floating gate; and forming a control gate on the second gate insulating film so as to overlap the floating gate in the longitudinal direction A step of forming source and drain regions by doping an exposed portion of the semiconductor substrate with an impurity of a conductivity type different from that of the semiconductor substrate using the control gate as a mask; An insulating film is formed to cover the control gate, And a step of forming a select gate, and poly layer on both sides of the control gate.

In forming the floating gate, the polysilicon film is excessively etched to partially etch portions overlapping the photoresist pattern.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

Referring to FIGS. 2A to 2C, a process diagram showing a method of manufacturing a flash memory device according to the present invention is shown.

2A, a method of manufacturing a flash memory device according to the present invention forms a first gate insulating film 33 used as a tunnel oxide film on a semiconductor substrate 31 using a thermal oxidation method.

A polysilicon film is formed on the first gate insulating film 33 through a deposition method such as chemical vapor deposition to form a photoresist film on the polysilicon film. Then, the photoresist film is exposed and developed to form a photoresist pattern 36 that exposes the polysilicon film.

Then, the exposed portion of the polysilicon film is etched by an anisotropic etching method such as reactive ion etching using the photoresist pattern 36 as an etching mask to form an island-shaped floating gate 35 do.

At this time, the first gate insulating film 33 on the semiconductor substrate 31 is also etched to expose the semiconductor substrate 31. When forming the floating gate 35, the polysilicon film is overetched so that portions overlapping the photoresist pattern 36 are also etched so that the upper edge of the floating gate 35 is formed to have a round shape .

According to the present invention, by forming the floating gate 35 to have a rounded upper edge, it is possible to prevent the electric field from concentrating on the upper edge of the floating gate 35 when the manufactured flash memory device operates, Can be prevented.

Then, the photoresist pattern 36 is stripped and removed as shown in Fig. 2B.

Then, a second gate insulating film 37 is formed on the semiconductor substrate 11 so as to cover the floating gate 35. The second gate insulating layer 37 may be formed to have an oxide-nitride-oxide (ONO) structure by sequentially depositing an oxide layer, a nitride layer, and an oxide layer by a deposition method such as chemical vapor deposition.

Then, polycrystalline silicon is deposited on the second gate insulating film 37 by CVD or the like, and then patterned by photolithography to form the control gate 39. At this time, the control gate 39 overlaps the island-shaped floating gate 35 with the second gate insulating film 37 therebetween, and is formed long in the longitudinal direction.

Then, source and drain regions 41 and 43 are formed by doping the exposed portion of the semiconductor substrate 31 with the impurity of a conductivity type different from that of the semiconductor substrate 31 by using the control gate 39 as a mask.

Then, as shown in FIG. 2C, an insulating material such as silicon oxide is deposited on the semiconductor substrate 31 by CVD or the like to form the insulating film 45.

Subsequently, polycrystalline silicon is deposited on the insulating film 45 by CVD or the like. A deposited polycrystalline silicon is formed on both sides of the floating gate 35 and the control gate 39 by a select gate 47 in the form of a spacer and a poly layer 49 in the form of a drain region 43 and a source Regions 49 are formed.

At this time, the select gate 47 and the poly layer 49 are etched back by a method such as reactive ion etching so that the portion corresponding to the control gate 39 of the insulating film 45 is exposed. .

In the present invention, the select gate 47 formed in the form of a spacer on both sides of the surface, the floating gate 35 and the control gate 39 functions as a Fowler Nordheim electron tunneling (FN) tunneling when programming or erasing the floating gate 35 As a gate to cause a rise. Therefore, it is easy to program or erase the floating gate 35 by the select gate 47 as well as to reduce power consumption.

Since the select gate 47 is formed between the floating gate 35 and the drain region 43 so as to overlap with the drain region 43 on the side surface of the floating gate 35, a short channel effect due to 'turn on' can be prevented.

As described above, according to the present invention, a first gate insulating film is formed on a semiconductor substrate, polycrystalline silicon is deposited on the first gate insulating film, and is patterned in an island shape. During patterning, excessive etching is performed to partially overlap the photoresist pattern The rounded top edge forms a floating gate.

Then, a control gate is formed to be long in the longitudinal direction so as to overlap with the control gate through the second gate insulating film, and an insulating film covering the control gate is formed on the semiconductor substrate. Then, Are formed so as to overlap with the drain region and the source region, respectively.

Therefore, the present invention can reduce power consumption while easily programming and erasing data in the floating gate, can prevent shortening of the device lifetime due to electric field concentration at the upper edge of the floating gate, There is an advantage that a short channel effect due to the short channel effect can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.

Claims (2)

A step of forming a first gate insulating film on a semiconductor substrate, Forming a floating gate by depositing polysilicon on the first gate insulating film and patterning the polysilicon so that the upper edge rounds in an island shape; Forming a second gate insulating film on the semiconductor substrate so as to cover the floating gate; Forming a control gate in the longitudinal direction so as to overlap the floating gate on the second gate insulating film; Forming a source and a drain region by doping an exposed portion of the semiconductor substrate with an impurity of a conductivity type different from that of the semiconductor substrate using the control gate as a mask; Forming an insulating film on the semiconductor substrate to cover the control gate, and forming select gates and a poly layer on both sides of the floating gate and the control gate. The method according to claim 1, Wherein the floating gate is etched to include a portion overlapping the photoresist pattern by overetching the polysilicon film.

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