KR100470184B1 - Flash memory device and its manufacturing method - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device having an advantage of a split gate type and a method of manufacturing the same.

2. Technical problem that the invention tries to solve

In a conventional split gate type flash memory device, a select gate serves to increase program efficiency. However, since one more gate is formed, a peripheral circuit for selectively operating the gate must be added. Since the loading of the select gate is large, high-speed access is difficult, and the selection gate and the floating gate Since the potential is kept different, it is intended to solve the problem such as loss of charge.

3. Summary of the solution of the invention

The flash memory device is configured such that the floating gate serves as the select gate at the same time.

4. Important uses of the invention

Applied in flash memory device fabrication of semiconductor devices.

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device having an advantage of a split gate type and a method of manufacturing the same.

In general, a flash memory device is classified into a stack gate type and a split gate type according to the type of the gate electrode of the memory cell.

A conventional split gate type flash memory device manufacturing method will be briefly described with reference to FIG. 1 as follows.

Referring to FIG. 1, a tunnel oxide film 2, a floating gate 3, and a dielectric film 4 are formed on a semiconductor substrate 1 through an etching process using a floating gate mask and a self-aligned etching process using a control gate mask. ) And a stacked gate in which the control gate 5 is stacked. After the stacked gate is formed, the source 9 and the drain 8 are formed by an ion implantation process using a cell source / drain mask, and then an oxide layer 6 is formed, followed by an etching process using a select gate mask. The select gate 7 is formed on the entire upper surface.

In the above-described conventional split gate type flash memory device, the select gate 7 assists generation of a hot carrier during programming, thereby improving program efficiency and preventing excessive erasing problems. However, since there is one more select gate 7, a peripheral circuit for selectively operating the select gate 7 needs to be added. Since the load of the select gate 7 is large, high-speed program access is difficult. Since the potentials of the select gate and the floating gate remain different, the loss of charge causes a problem in the reliability of the device.

Accordingly, an object of the present invention is to provide a flash memory device and a method of manufacturing the same, in which a floating gate can simultaneously serve as a select gate so that the above-mentioned problems can be solved, thereby simplifying the process.

In the flash memory device according to the present invention for achieving the above object, a floating gate formed on a semiconductor substrate and electrically separated from the semiconductor substrate by a tunnel oxide film and a selective oxide film, and a dielectric film on the floating gate; And a control gate electrically separated from each other, and a source and a drain formed on both sides of the floating gate.

In the method of manufacturing a flash memory device according to the present invention, a silicon nitride film, a first polysilicon film and a tunnel oxide film are formed by sequentially forming and patterning a tunnel oxide film, a first polysilicon film and a silicon nitride film on a semiconductor substrate. Forming a stacked pattern; Forming an insulating film spacer on both sides of the pattern, and then forming a selective oxide film on the semiconductor substrate on both sides of the insulating film spacer; Removing the silicon nitride layer to expose the patterned first polysilicon layer, forming a second polysilicon layer on the entire upper surface, and then patterning to form a floating gate of the first and second polysilicon layers; And forming a source and a drain on both sides of the floating gate, and then sequentially forming a dielectric film and a control gate on the entire upper surface thereof.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views of a flash memory device and a device for manufacturing the same according to the present invention.

Referring to FIG. 2A, the tunnel oxide layer 12, the polysilicon layer for the first floating gate 13, and the silicon nitride 14 are sequentially formed on the semiconductor substrate 11, and then etched using a mask for the floating gate. The first floating gate 13 is formed through the process. After that, the insulating film spacers 15 are formed on both sidewalls of the silicon nitride 14, the first floating gate 13, and the tunnel oxide film 12.

Referring to FIG. 2B, after forming the selective oxide layer 16 on both sides of the insulating layer spacer 15, the entire surface etching process is performed until the first floating gate 13 is exposed. Thereafter, a polysilicon layer 17 is formed on the entire upper surface.

Referring to FIG. 2C, the polysilicon layer 17 is patterned by a mask and an etching process at a position where a portion of the first floating gate 13 and the selective oxide film 16 overlap with each other to form a second floating gate 17A pattern. At the same time, the remaining selective oxide film 16, the tunnel oxide film 12, the insulating film spacer 15, and a part of the first floating gate 13 are removed to expose the semiconductor substrate 11. As a result, the selective oxide film 16, the insulating film spacer 15, and the first floating gate 13 are formed under the second floating gate 17A.

Subsequently, the source 20 and the drain 21 are formed on both sides of the first floating gate 13 and the selective oxide film 16 in a self-aligned manner, and then an oxidation process is performed on the entire upper surface of the dielectric film 20 and An oxide film 19 is formed. Thereafter, the control gate 22 is formed on the entire upper surface. At this time, the coupling ratio between the first and second floating gates 13 and 17A and the control gate 22 is 0.6.

When a high voltage of about 10V is applied to the control gate 22 during programming of the above-described flash memory device, a channel is formed in the selective oxide layer 16 and current flows, and a hot carrier is formed in the insulating layer spacer 15 region. Is generated and programmed.

During program erasing, a high voltage of about -10V is applied to the drain 21 region to discharge electrons out of the floating gate, and the readout is performed by applying a voltage of about 5V to the control gate 22 during reading.

As described above, since the first and second floating gates act as select gates, the circuit is simple, the program and erase can be performed at a relatively low gate voltage, and there is no risk of losing the floating gate charge, resulting in improved device reliability. do.

1 is a cross-sectional view of a device for explaining a conventional flash memory device manufacturing method.

2A to 2C are cross-sectional views of devices for explaining a method of manufacturing a flash memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

1 and 11: semiconductor substrate 2 and 12: tunnel oxide film

3: floating gate 4 and 18: dielectric film

5 and 22; Control gates 6 and 19: oxide film

7: select gate 13: first floating gate

14 silicon nitride film 15 insulating film spacer

16: selective oxide film 17: polysilicon layer

17A: second floating gate 9 and 20: source

8 and 21: drain

Claims (4)

In the flash memory device manufacturing method, Sequentially forming and patterning a tunnel oxide film, a first polysilicon film, and a silicon nitride film on a semiconductor substrate to form a pattern in which a silicon nitride film, a first polysilicon film, and a tunnel oxide film are stacked; Forming an insulating film spacer on both sides of the pattern, and then forming a selective oxide film on the semiconductor substrate on both sides of the insulating film spacer; The first and second polysilicon layers are removed by exposing the patterned first polysilicon layer by removing the silicon nitride layer, forming a second polysilicon layer on an entire upper surface thereof, and patterning the first polysilicon layer to partially overlap the first polysilicon layer. Forming a floating gate; And And forming a source and a drain on both sides of the floating gate, and then sequentially forming a dielectric film and a control gate on the entire upper surface thereof. The method of claim 1, And the floating gate is electrically separated from the semiconductor substrate by the tunnel oxide film and the selective oxide film, respectively. The method of claim 1, The source and drain are formed by a self-aligning method. The method of claim 1, And the floating gate serves as a select gate in the select oxide layer.

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