KR100423577B1 - Manufacturing Method of Flash Memory Device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a flash memory device.

2. Technical problem to be solved by the invention

In the conventional method of manufacturing a flash memory device, since the cell spacer has an ON structure, the select gate and the cell spacer nitride film contact with each other, and electrons or holes flow into the cell spacer nitride film from the select gate, thereby degrading device characteristics and device life.

3. Summary of the Solution of the Invention

In order to form a cell spacer, a polysilicon film is formed on the cell spacer formed of an oxide film and a nitride film, and then oxidized and converted into a polyoxide film to form a cell spacer having an oxide film, a nitride film, and a polyoxide film structure.

4. Important uses of the invention

Method for manufacturing all semiconductor devices using spacers.

Description

Manufacturing Method of Flash Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a flash memory device capable of increasing device reliability by forming an ONO structure cell spacer during a split gate type flash EEPROM.

In general, a split gate type flash EEPROM has a structure in which a stack cell between a source and a drain and a normal transistor are connected in parallel. There are two types of gate oxide films used in a split transistor and a tunnel oxide film used for erase in a stack cell. Gate oxide film is used. In this case, the cell spacer may be made of only an oxide film and a nitride film, so that the select gate polysilicon film and the cell spacer nitride film are in direct contact. Thus, a hole may be introduced into the spacer nitride film or the floating gate from the polysilicon film for the select gate under certain conditions during harsh experiments or retention stresses that only continuously read for a long time. Therefore, if possible, the cell spacer should be made into an ONO structure to improve it. However, since the oxide layer on the cell spacer nitride layer is completely removed in the wet oxide removal process, which is a process before forming the gate gate split after forming the cell spacer, the ONO structure cannot be formed.

A method of fabricating a general split gate type flash memory device will be described with reference to FIGS. 1A through 1G as follows.

FIG. 1A illustrates a field oxide film 12 for separating cell region A and peripheral circuit regions B and C on a silicon substrate 11 having a well region formed by an impurity ion implantation process. To grow. The tunnel oxide film 13 and the first polysilicon film 14 for floating gate in the cell region are formed over the entire structure. In this example, the peripheral circuit region is formed of a high voltage transistor region B and a low voltage transistor region C, and the high potential transistor region is a high potential NMOS and a high potential PMOS, a low potential transistor. The region is formed of low potential NMOS, low potential PMOS. After the photoresist is applied over the entire structure, an exposure and etching process using a mask that opens only the cell region is performed to form a first photoresist pattern (not shown). The first polysilicon layer 14 is etched using the first photoresist pattern (not shown) to expose the field oxide layer 12 separating the cell region and the peripheral circuit region. At this time, the width of the cell region is determined.

As shown in FIG. 1B, a dielectric film 15, a second polysilicon film 16, and an oxide film 17 are formed over the entire structure. The second polysilicon film 16 is used as a control gate to which a high potential is applied during programming or erasing. The second photoresist pattern 18 is formed by applying an interfacial film over the entire structure and then performing exposure and development using a self-aligned etching mask.

As shown in FIG. 1C, an etch process is performed using the second photoresist pattern 18 as a mask to form an oxide layer 17, a second polysilicon layer 16, a dielectric layer 15, and a first polysilicon layer. 14 is sequentially removed to form a stack gate structure in the cell region. At this time, the peripheral circuit region is all open, and after etching, all the stacked layers are removed. After removing the second photoresist pattern 18 and applying the photoresist again, the third photoresist pattern 19 is formed by an exposure and shape process using a cell source / drain mask. An impurity ion implantation process is performed using the third photoresist pattern 19 as a mask to form the source 20a, 20b and drain 21 regions in the selected region of the silicon substrate 11 in the cell region. In this case, the drain region 21 is self-aligned by the stack gate formed by the second photoresist pattern 18, and the source regions 20a and 20b are defined by the third photoresist pattern 19.

As shown in FIG. 1D, the first photoresist layer 22 is formed by removing the third photoresist pattern 19 and then applying a poly oxide process or an oxide film. A nitride film is coated on the first interlayer insulating film 22 to form a second interlayer insulating film 23. After the photoresist is applied over the entire structure, the fourth photoresist pattern 24 is formed by an exposure and development process using a high voltage mask. An etching process is performed using the fourth photoresist pattern 24 as a mask to etch the high potential transistor region, that is, the high potential NMOS and high potential PMOS regions, to expose the silicon substrate 11. At this time, the oxide film used as the first interlayer insulating film 22 and the nitride film using the second interlayer insulating film 23 become actual cell spacers in a subsequent process, and the purpose of the fourth photoresist film 24 by the high potential mask is subsequent etching. It is used for the purpose of selectively making a thick gate oxide film of a high potential peripheral circuit which generates a high potential by a process.

As shown in FIG. 1F, after the fourth photoresist pattern 24 is removed, only the high potential gate oxide layer 25 is selectively formed using the characteristics of the nitride film used as the second interlayer insulating layer 23. After the photoresist is applied over the entire structure, the fifth photoresist pattern 26 is formed by an exposure and development process using a cell spacer mask. An etching process is performed using the fifth photoresist layer pattern 26 as a mask to form cell spacers 27 formed of oxide and nitride layers of the first and second interlayer insulating layers 22 and 23 on the sidewalls of the stack gate structure. In the cell region, a gate oxide film (not shown) used for a general transistor is formed in the select gate oxide film 28 and the low potential transistor region, that is, the low potential NMOS and low potential PMOS regions. At this time, a wet oxide film removal process is performed to cleanly remove the tunnel oxide film 13 remaining on the surface of the silicon substrate. This process removes the select gate oxide film even if the cell spacer nitride film is applied and then the select gate oxide film is applied. There is no choice but to be.

As shown in FIG. 1F, after the fifth photosensitive layer pattern 26 is removed, the low potential gate oxide layer 29 is formed. A third polysilicon film 30 and a tungsten silicide film 31, which serve as gates of actual peripheral circuits and select gates of cell regions, are sequentially formed on the entire structure. At this time, the final thickness of the high potential gate oxide film 25 is determined by the oxide film formation process. Subsequent portions of the peripheral circuit transistor and the select gate forming and interconnecting processes are omitted, and a portion of the threshold voltage regulating ion implantation process in the cell region is also omitted.

As described above, since the cell spacer having the ONO structure cannot be formed by the conventional method, the select gate and the cell spacer nitride film are in contact with each other, so that electrons or holes can be injected from the select gate into the spacer nitride film, and the injected charges And reliability associated with device lifetime.

Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of improving the lifespan and reliability of the device by forming the cell spacer of the ONO structure.

The present invention for achieving the above object is to form a field oxide film on a silicon substrate to separate into a cell region, a high potential transistor region and a low potential transistor region, forming a tunnel oxide film on the cell region and the tunnel oxide film Forming a gate structure in which the first polysilicon film, the dielectric film, the second polysilicon film, and the oxide film are sequentially stacked on the selected region, and performing an impurity ion implantation process on the selected region of the cell region, Forming a drain region, sequentially forming a first interlayer insulating film and a second interlayer insulating film over the cell region, and forming a high potential gate oxide film over the high potential transistor region, and then forming the cell region and the high Forming a polysilicon film for a cell spacer on the upper transistor region; Etching the selected regions of the cell spacer polysilicon film, the second interlayer insulating film, and the first interlayer insulating film formed on the substrate to form a spacer; removing the polysilicon film for cell spacer formed on the high potential transistor region; When the entire structure is oxidized to form a select gate oxide film in the cell region and a low level gate oxide film in the low level transistor region, the polysilicon film for the cell spacer is changed into a polyoxide film, and a third polysilicon film and And forming tungsten silicide.

The present invention will be described in detail with reference to the accompanying drawings.

2 (a) to 2 (i) are cross-sectional views of devices for explaining a method of manufacturing a flash memory device according to the present invention.

FIG. 2 (a) shows a field oxide film for separating cell region A ′ and peripheral circuit regions B ′ and C ′ on a silicon substrate 41 having a well region formed by an impurity ion implantation process. 42) grow. The tunnel oxide film 43 and the first polysilicon film 44 for floating gate in the cell region are formed on the entire structure. In this example, the peripheral circuit region is formed of a high voltage transistor region B 'and a low voltage transistor region C'. The high potential transistor region is formed of a high potential NMOS and a high potential PMOS, and the low potential transistor region is formed of a low potential NMOS and a low potential PMOS. After the photoresist is applied over the entire structure, an exposure and etching process using a mask that opens only the cell region is performed to form a first photoresist pattern (not shown). The first polysilicon film 44 is etched using the first photoresist pattern (not shown) to expose the field oxide film 42 separating each of the cell region and the peripheral circuit region. At this time, the width of the cell region is determined.

As shown in FIG. 2B, a dielectric film 45, a second polysilicon film 46, and an oxide film 47 are formed over the entire structure. The second polysilicon film 46 is used as a control gate to which a high potential is applied during programming or erasing. After the photoresist is applied over the entire structure, the second photoresist pattern 48 is formed by an exposure and development process using a self-aligned etching mask.

As shown in FIG. 2C, an etching process is performed using the second photoresist pattern 48 as a mask to form an oxide film 47, a second polysilicon film 46, a dielectric film 45, and a first polysilicon film. 44 is sequentially removed to form a stack gate structure in the cell region. At this time, the peripheral circuit region is all open, and after etching, all the stacked layers are removed. After removing the second photoresist pattern 48 and applying the photoresist again, the third photoresist pattern 49 is formed by an exposure and shape process using a cell source / drain mask. An impurity ion implantation process is performed using the third photoresist pattern 49 as a mask to form the source 50a, 50b and drain 51 regions in the selected region of the silicon substrate 41 in the cell region. In this case, the drain region 51 is self-aligned by the stack gate formed by the second photoresist pattern 48, and the source regions 50a and 50b are defined by the third photoresist pattern 49.

As shown in FIG. 2 (d), the first photoresist layer 52 is formed by removing the third photoresist pattern 49 and applying a poly oxidization process or an oxide film. A nitride film is coated on the first interlayer insulating film 52 to form a second interlayer insulating film 53. After the photoresist is applied over the entire structure, the fourth photoresist pattern 54 is formed by an exposure and development process using a high voltage mask. An etching process is performed using the fourth photoresist pattern 54 as a mask to etch the high potential transistor region, that is, the high potential NMOS and high potential PMOS regions, to expose the silicon substrate 41. At this time, the oxide film used as the first interlayer insulating film 52 and the nitride film using the second interlayer insulating film 53 become actual cell spacers in a subsequent process, and the fourth photosensitive film 54 by the high potential mask is subjected to the subsequent etching process. It is used for the purpose of selectively making a thick gate oxide film of a high potential peripheral circuit which generates a high potential.

As shown in FIG. 2E, after removing the fourth photoresist pattern 54, the high potential gate oxide layer 55 is formed in the high potential transistor region, and then the cell spacer polysilicon layer 56 is coated on the entire structure. do. After the photoresist is applied over the entire structure, an exposure and etching process using a cell spacer mask is performed to form a fifth photoresist pattern 57. An etching process is performed using the fifth photoresist pattern 57 as a mask to form the cell spacers 58, and then a wet oxide film removal process is performed. In this case, the cell spacer includes an oxide film, a nitride film, and a polysilicon film.

As shown in FIG. 2 (f), after the fifth photoresist pattern 57 is removed, a photoresist is applied over the entire structure, and an exposure and development process using a cell spacer polysilicon removal mask is performed to perform the sixth photoresist pattern 59. ). The sixth photoresist pattern 59 is subjected to a wet etching process to remove the cell spacer polysilicon layer 56 formed in the high potential transistor region.

As shown in FIG. 2G, the select gate oxide layer 60 is formed in the cell region and the low potential gate oxide layer 61 is formed in the low potential transistor region after the sixth photoresist pattern 59 is removed. In the cell spacer 58, the polysilicon is oxidized in the oxide film, nitride film, and polysilicon film structure to be converted into the polyoxide film 56a, thereby forming an ONO structure. A third polysilicon film 62 and a tungsten silicide film 63 used as a select gate are sequentially formed on the entire structure.

As an exemplary embodiment of the present invention, a split gate type flash memory including three polysilicon films has been described, but the present invention is not limited thereto. For example, a split gate type flash memory including two polysilicon films may be used. It can be extended to the whole range of ONO spacer.

As described above, according to the present invention, by forming the cell spacer in the ONO structure, the inflow of charge into the trap center of the spacer nitride film can be suppressed to increase the reliability of the device, and in particular with respect to data retention and data gain. The characteristics through the paths of the select gate and the floating gate can be improved.

1 (a) to 1 (g) are cross-sectional views of a device for explaining a method of manufacturing a conventional split gate type flash memory device.

2 (a) to 2 (i) are cross-sectional views of a device for explaining a method of manufacturing a flash memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

A, A ': cell region B, B': high level transistor region

C, C ': low-level transistor region

11, 41: silicon substrate 12, 42: field oxide film

13, 43: tunnel oxide film 14, 44: first polysilicon film

15, 45: dielectric film 16, 46: second polysilicon film

17, 47: oxide film 18, 48: second photosensitive film pattern

19 and 49: third photoresist pattern 20a and 20b, 50a and 50b: source region

21, 51: drain region 22, 52: first interlayer insulating film

23, 53: second interlayer insulating film 24, 54: fourth photosensitive film pattern

25, 55: high potential gate oxide film 26, 57: fifth photosensitive film pattern

27, 58: cell spacer 28, 60: select gate oxide film

29, 61: low potential gate oxide film 30, 62: third polysilicon film

31, 63: tungsten silicide film 58: cell spacer

58a: polyoxide film 59: sixth photosensitive film pattern

Claims (1)

Forming a field oxide film on the silicon substrate to distinguish the cell region, the high potential transistor region, and the low potential transistor region; Forming a tunnel oxide film over the cell region and forming a gate structure in which a first polysilicon film, a dielectric film, a second polysilicon film, and an oxide film are sequentially stacked in a selected region over the tunnel oxide film; Forming a source and a drain region by performing an impurity ion implantation process in a selected region of the cell region; Sequentially forming a first interlayer insulating film and a second interlayer insulating film over the cell region; Forming a high potential gate oxide layer on the high potential transistor region, and then forming a polysilicon layer for cell spacers on the cell region and the high potential transistor region; Etching the selected regions of the polysilicon film for the cell spacer, the second interlayer insulating film, and the first interlayer insulating film formed in the cell region to form a spacer; Removing the polysilicon film for cell spacer formed on the high potential transistor region; Converting the polysilicon film for the cell spacer into a polyoxide film when the entire structure is oxidized to form a select gate oxide film in the cell region and a low level gate oxide film in the low level transistor region; And forming a third polysilicon film and tungsten silicide on the entire structure.

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