KR19990060867A - Stack gate formation method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a stack gate forming method capable of simultaneously forming a gate of a peripheral circuit and a cell using a gate mask.

2. Technical problem to be solved by the invention

The conventional stack gate formation method causes a problem in reliability characteristics such as data retention capability because the mask process of several steps is performed after the formation of the ONO film, and since the peripheral circuit and the cell gate are etched separately, a constant margin is formed when forming the contact hole. Required.

3. Summary of the Solution of the Invention

The present invention is to reduce the number of processes by simultaneously forming the gate of the peripheral circuit and the cell using a gate mask.

4. Important uses of the invention

Semiconductor device manufacturing process

Description

Stack gate formation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a stack gate forming method capable of simultaneously forming a gate of a peripheral circuit and a cell using a gate mask.

In general, a flash Y-pyrom cell device having an electrical program and erase function is composed of a peripheral circuit and a memory cell array. The memory cell array includes a plurality of memory cells each selected by a word line and a bit line signal. A program operation for storing data in a memory cell is performed by injecting a hot electron into a floating gate, and an erase operation for erasing stored information is injected into the floating gate. By causing the electrons to be lost. In addition, the memory cell is divided into a stack gate and a split gate according to the shape of the gate electrode. Here, a typical manufacturing process for a conventional stack cell flash EEPROM is roughly described. Let's explain.

The stack gate forming method of the conventional first method is as follows.

After forming the sacrificial oxide film on the silicon substrate, ion implantation for adjusting the threshold voltage of the peripheral circuit is performed, and after forming the gate oxide film for high voltage, a first mask process for defining the cell region is performed. Thereafter, after the ion implantation for adjusting the threshold voltage of the cell region is performed, the oxide film is removed, the tunnel oxide film and the first polysilicon are sequentially stacked, and then the doping process is performed. The first polysilicon is patterned using a second mask to define a high voltage gate and a memory cell region. Subsequently, after the dielectric film is deposited, the dielectric film in the peripheral circuit region is removed using a third mask to form a low voltage gate oxide film. Thereafter, a second polysilicon deposition and doping process is performed, and a tungsten silicide layer and a thick arc layer are sequentially stacked, followed by gate etching using a fourth mask for forming a low voltage gate and a cell, and a fifth After opening the cell region using a mask, the first polysilicon of the cell is etched using the arc layer.

The conventional first method requires a five-step mask process until the gate is formed, and since the gate of the high-voltage transistor is formed in the etching process of the first polysilicon layer, the gate of the high-low voltage transistor cannot be formed of silicide and thus delayed. The speed decrease by delay may be a concern. In addition, the formation mask process of the high voltage transistor and the cell and the low voltage transistor is separated, so that a margin of a gate related design rule, such as a space between the contact hole and the gate, is required in forming a subsequent metal layer contact.

In addition, in the conventional second method, the process before forming tungsten silicide is the same as the method of the first, and after the deposition of the thin arc layer, the gate is etched using the fourth mask for forming the low voltage gate. Thereafter, after forming the cell gate using the fifth mask, an etching process for forming the cell stack gate is performed.

The second method described above requires the same mask step as the first method, and still has the disadvantage that the high voltage transistor is a non-silicide gate. In addition, since the gates of the cell and the high voltage and the low voltage are separately formed, the margin of the gate related design rule such as the space between the contact hole and the gate becomes more problematic than the first method. However, there is an advantage that the thickness of the arc layer can be lowered, which helps to form a contact on the gate.

In the third conventional method, after forming a sacrificial oxide film, a cell region is defined using a first mask, and ion implantation for cell threshold voltage is performed. After removing the oxide film and depositing the tunnel oxide film, the first polysilicon is deposited and a doping process is performed. The first polysilicon of the cell region is defined using the second mask, and after the dielectric film is deposited, the dielectric film of the peripheral circuit region is removed using a third mask for removing the dielectric film of the peripheral circuit region. After the threshold voltage ion implantation is performed, a high voltage gate oxide film is deposited, a low voltage transistor is defined using a fourth mask, and the oxide film is removed. After depositing the low-voltage gate oxide film, a second polysilicon is deposited and a doping process is performed.

Subsequent processes may use two methods such as cell definition using a thick arc layer or etching peripheral circuits and cell regions separately, as in the first and second methods. The advantage of this method is that the gates of the peripheral circuit transistors are all made of second polysilicon so that tungsten silicide gates can be used. However, at least two to three mask steps are applied after the deposition of the dielectric film, which adversely affects the characteristics of the dielectric film, which may cause problems in reliability characteristics such as data retention capability. Also, if a thin arc layer is used to etch the peripheral circuit and cell gate separately, contact-related design rules still require margin. In addition, there is a disadvantage that the mask process is increased by one step than the first and second methods.

As described above, the conventional process includes a tunnel oxide film process and there are three gate oxide film processes. This is because there are transistors with three kinds of gate oxide films. If the gate oxide film for high voltage or low voltage has the same thickness as the tunnel oxide film, the gate oxide process can be reduced to two times and the manufacturing process of the peripheral circuit will be easier. Can be. If the operating voltage of the device is lowered so that the gate oxide film of the low voltage device can be used together with the tunnel oxide film thickness, the problem of the conventional method described above can be solved.

Therefore, in order to solve the above-mentioned problems, the present invention solves the gate of the peripheral circuit with the same layer by depositing the first polysilicon while all three kinds of oxide films are grown, and removes the dielectric film of the peripheral circuit region. In order to deposit polysilicon so that the gate topology of the cell and the peripheral circuit except the dielectric film is completely the same, the gate of the peripheral circuit and the cell may be simultaneously formed using a gate mask. In the first polysilicon etching process, only the cell pattern for forming the floating gate is formed and the gate of the cell and all the transistors are formed in the gate etching process, thereby reducing the burden of misalignment between the contact hole and the gate. .

According to an aspect of the present invention, a sacrificial oxide film is formed on a silicon substrate of a peripheral circuit region including a memory cell forming region, a high voltage transistor, and a low voltage transistor forming region, and then the peripheral circuit region and the memory cell region. Implanting a threshold voltage into the silicon substrate of the silicon substrate, removing the sacrificial oxide film, and forming a first oxide film on the silicon substrate, and forming a low voltage transistor forming region and a memory cell region of the peripheral circuit region. Patterning the first oxide film to expose the silicon substrate, and forming a tunnel oxide film and a second oxide film on the silicon substrate in the memory cell region and the low voltage transistor forming region, and then the memory cell region and the peripheral circuit. On the tunnel oxide film and the first and second oxide films formed in the region Forming a first polysilicon layer, patterning a field region of the first polysilicon layer, depositing a dielectric film on the first polysilicon layer, and patterning the first polysilicon layer in the peripheral circuit region to be exposed And sequentially stacking a second polysilicon layer, a tungsten silicide layer, and an arc layer on the entire structure, and forming a photoresist pattern, and a peripheral circuit region of the memory cell region and the high voltage and low voltage formation region. Sequentially patterning the arc layer, the tungsten silicide layer, and the second polysilicon layer to expose the dielectric film and the first polysilicon layer of the silicon film; Patterning the dielectric film and the first polysilicon layer to expose the memory cell, the high voltage transistor, and the low It characterized in that made in a step of forming a transistor.

1 (a) to 1 (g) are cross-sectional views illustrating a stack gate forming method according to the present invention.

<Description of Signs of Major Parts of Drawings>

1: silicon substrate 2: first oxide film

3: tunnel oxide film 4: second oxide film

5, 7: polysilicon 6: dielectric film

8: tungsten silicide 9: arc layer

10: Photoresistor

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (g) are cross-sectional views illustrating a stack gate forming method according to the present invention.

FIG. 1A illustrates a sacrificial oxide film formed on a silicon substrate of a peripheral circuit region PH including a memory cell region MC, a high voltage transistor and a low voltage transistor formation region, and then the peripheral circuit region PH and It is sectional drawing of the state which threshold-voltage ion implantation was performed to the said silicon substrate 1 of the memory cell area MC.

FIG. 1B illustrates a first oxide film 2 formed on the silicon substrate 1 after removing the sacrificial oxide film, and a low voltage transistor forming region and the memory cell region MC of the peripheral circuit region PH. It is sectional drawing of the state which patterned the said 1st oxide film 2 so that the said silicon substrate 1 might be exposed.

FIG. 1C illustrates a tunnel oxide film 3 and a second oxide film 4 formed on the silicon substrate 1 in the memory cell region MC and the low voltage transistor formation region, and then the memory cell region ( It is sectional drawing of the state in which the 1st polysilicon layer 5 was formed on the said tunnel oxide film 3 and the 1st and 2nd oxide films 2 and 4 formed in MC and the peripheral circuit area | region PH. At this time, since the tunnel oxide film 3 and the second oxide film 4 have the same thickness, they are grown at the same time.

FIG. 1D illustrates the patterning of the field region of the first polysilicon layer 5, and a dielectric film (eg, on the first polysilicon layer 5 of the memory cell region MC and the peripheral circuit region PH). 6) is a cross-sectional view of the state in which the first polysilicon layer 5 of the peripheral circuit region PH is patterned so as to be exposed.

FIG. 1 (e) shows a state in which a photoresist pattern 10 is formed after sequentially stacking a second polysilicon layer 7, a tungsten silicide layer 8, and an arc layer 9 on the entire structure. It is a cross section. In this case, the polysilicon doping process is performed after the first and second polysilicon layers 5 and 7 are formed. In addition, in the deposition of the first and second polysilicon layers 5 and 7, it is possible to deposit IN-SITU doped polysilicon.

FIG. 1F illustrates the arc layer 9 so that the dielectric film 6 and the first polysilicon layer 5 of the memory cell region MC and the peripheral circuit region PH of the high voltage and low voltage formation region are exposed. It is sectional drawing which shows the state which patterned the tungsten silicide layer 8 and the 2nd polysilicon layer 7 sequentially.

FIG. 1G illustrates the dielectric film 6 and the first polysilicon layer 5 to expose the silicon substrate 1 of the memory cell region MC and the peripheral circuit region PH of the high voltage and low voltage formation region. Is a cross-sectional view illustrating a state in which the memory cell MC, the high voltage transistor HV, and the low voltage transistor LV are formed by patterning the semiconductor cells.

After performing the etching process for forming the gate electrode, a thermal process for alleviating damage of the oxide film generated during etching is performed. Thereafter, an ion implantation step for forming a source of the cell is performed, followed by ion implantation necessary for forming a peripheral circuit, and then forming a contact and a metal wiring. A precondition for applying the above invention should be a gate oxide film of a peripheral circuit having the same thickness as the tunnel oxide film. Accordingly, the present invention is applicable to a case where there is a transistor of a peripheral circuit in which the operation voltage is reduced and the thickness of the gate oxide film is contracted so that the device can be driven at the same thickness as the tunnel oxide film.

The present invention also includes the doping of the first and second polysilicon with POCl ₃ doping or with in-situ polysilicon deposition.

As described above, the present invention has the following excellent effects.

First, since all the gates of the peripheral circuits form the second polysilicon layer and gate etching is performed by defining the gates of the cell and the peripheral circuits at once, all transistors can be formed of tungsten silicide gates, requiring high speed. Suitable for technical trends Also, in implementing this, since the cell and the peripheral circuit are formed through one etching at the same time without increasing the number of mask processes, the etching process is advantageous in terms of the gate related design rule of the space between the contact hole and the gate. .

Second, when the tungsten silicide gate is to be implemented in all transistors, the mask step exposure problem of the dielectric film, which is a problem in the conventional method, is minimized, so that the mask film is subjected to one mask process in the state where the dielectric film is exposed.

Third, since the stack gate of the cell is formed by using the gate etching mask, the thickness of the arc layer used for the etching hard mask for performing the first polysilicon etching of the conventional cell may be reduced. Reducing the thickness of the arc layer can facilitate the etching process of the metal contacts formed on the gate. In addition, since the gate topology of the cell and the peripheral circuit is the same, the step difference between the cell and the peripheral circuit after the BPSG flow can be reduced.

Fourth, the gate electrode configuration of the peripheral circuit is composed of the first and second polysilicon and the like, so that the doping level of the gate electrode is uniform regardless of the type of transistor.

Fifth, when S.A.S etching is performed in a subsequent process, there is a possibility that morphological growth of tungsten silicide occurs due to an attack caused by S.A.S etching, and a process of covering polysilicon on tungsten silicide is necessary to prevent this. However, by controlling the thickness of the arc layer so that the arc layer remains after the S.A.S etching, the growth of the tungsten silicide layer can be prevented without the addition of the polysilicon layer.

Claims (1)

After the threshold voltage adjustment ion implantation is performed on the silicon substrate of the peripheral circuit forming region including the memory cell forming region and the high voltage transistor and low voltage transistor forming region, a patterned first oxide film is formed on the high voltage transistor forming region. To do that, After a tunnel oxide film and a second oxide film are formed on the silicon substrate in the memory cell formation region and the low voltage transistor formation region, a first polysilicon layer is formed on the entire structure, and then a patterned dielectric film is formed on the memory cell. Forming in the formation region; After sequentially stacking a second polysilicon layer, a tungsten silicide layer and an arc layer on the entire structure, the dielectric film and the first poly in the peripheral circuit forming region of the memory cell forming region and the high voltage and low voltage transistor forming region. Sequentially patterning the arc layer, the tungsten silicide layer, and the second polysilicon layer to expose a silicon layer; Patterning the dielectric film and the first polysilicon layer to expose the silicon substrate in the peripheral circuit forming region of the memory cell forming region and the high voltage and low voltage transistor forming region to form a memory cell, a high voltage transistor, and a low voltage transistor Stack gate forming method comprising a.