KR970053057A - Method of manufacturing transistor of semiconductor device - Google Patents

Method of manufacturing transistor of semiconductor device Download PDF

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Publication number
KR970053057A
KR970053057A KR1019950065670A KR19950065670A KR970053057A KR 970053057 A KR970053057 A KR 970053057A KR 1019950065670 A KR1019950065670 A KR 1019950065670A KR 19950065670 A KR19950065670 A KR 19950065670A KR 970053057 A KR970053057 A KR 970053057A
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KR
South Korea
Prior art keywords
forming
entire structure
region
etching
transistor
Prior art date
Application number
KR1019950065670A
Other languages
Korean (ko)
Other versions
KR0172041B1 (en
Inventor
장상환
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950065670A priority Critical patent/KR0172041B1/en
Publication of KR970053057A publication Critical patent/KR970053057A/en
Application granted granted Critical
Publication of KR0172041B1 publication Critical patent/KR0172041B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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  • Non-Volatile Memory (AREA)

Abstract

본 발명은 고전압 및 저전압용 트랜지스터의 절연막을 각각 독립된 공정으로 형성하므로서 불순물에 의한 오염 및 절연 특성을 향상시킬 수 있는 반도체 소자의 트랜지스터 제조 방법이 개시된다.Disclosed is a method of fabricating a transistor of a semiconductor device capable of improving contamination and insulation characteristics due to impurities by forming insulating films of high voltage and low voltage transistors in separate processes.

Description

반도체 소자의 트랜지스터 제조 방법Method of manufacturing transistor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a 내지 1g도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도.1A to 1G are cross-sectional views illustrating a transistor manufacturing method of a semiconductor device according to the present invention.

Claims (1)

반도체 소자의 트랜지스터 형성 방법에 있어서, 실리콘 기판상에 터널 산화막 및 제1폴리 실리콘을 형성하는 단계와, 상기 전체 구조 상부에 식각 공정에 의해 셀 영역이 제외된 제1트랜지스터 및 제2트랜지스터 영역을 식각하는 단계와, 상기 전체 구조 상부에 ONO층을 형성한 후, 상기 식각 공정에 의해 고전압 및 저전압 영역을 식각하는 단계와, 상기 전체 구조 상부에 제2폴리 실리콘층을 형성한 후, 식각 공정에 의해 셀 영역에 플로팅 게이트와 콘트롤 게이트를 형성하는 단계와, 상기 전체 구조 상부에 주변 회로 영역에 식각 공정에 의해 고전압 영역에 제1게이트 산화막을 형성하고, 동시에 저전압 영역에 제2폴리 실리콘층을 식각하는 단계와, 상기 셀 영역에 불순물을 주입하여 소오스 및 드레인 영역을 형성한 후, 상기 전체 구조 상부에 TEOS막을 증착하는 단계와, 상기 저전압 영역의 TEOS층을 패터닝 한 후, 제2 게이트 산화막을 성장하는 단계와, 상기 전체 구조 상부에 제3폴리 실리콘층을 형성하고, 상기 고전압 영역의 제3폴리 실리콘층을 식각 공정에 의해 패터닝하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.A method of forming a transistor of a semiconductor device, the method comprising: forming a tunnel oxide film and a first polysilicon on a silicon substrate, and etching the first transistor and the second transistor region from which a cell region is excluded by an etching process on the entire structure And forming an ONO layer on the entire structure, etching the high voltage and low voltage regions by the etching process, and forming a second polysilicon layer on the entire structure, followed by etching. Forming a floating gate and a control gate in a cell region, forming a first gate oxide film in a high voltage region by an etching process in a peripheral circuit region over the entire structure, and simultaneously etching a second polysilicon layer in a low voltage region And source and drain regions by implanting impurities into the cell region, and then forming a TEOS film over the entire structure. Contacting, patterning the TEOS layer in the low voltage region, growing a second gate oxide film, forming a third polysilicon layer over the entire structure, and forming a third polysilicon layer in the high voltage region A method for manufacturing a transistor of a semiconductor device, characterized by patterning by an etching process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065670A 1995-12-29 1995-12-29 Method of manufacturing transistor of semiconductor device KR0172041B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065670A KR0172041B1 (en) 1995-12-29 1995-12-29 Method of manufacturing transistor of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065670A KR0172041B1 (en) 1995-12-29 1995-12-29 Method of manufacturing transistor of semiconductor device

Publications (2)

Publication Number Publication Date
KR970053057A true KR970053057A (en) 1997-07-29
KR0172041B1 KR0172041B1 (en) 1999-03-30

Family

ID=19447134

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065670A KR0172041B1 (en) 1995-12-29 1995-12-29 Method of manufacturing transistor of semiconductor device

Country Status (1)

Country Link
KR (1) KR0172041B1 (en)

Also Published As

Publication number Publication date
KR0172041B1 (en) 1999-03-30

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