KR970003868A - Flash memory device manufacturing method - Google Patents

Flash memory device manufacturing method Download PDF

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Publication number
KR970003868A
KR970003868A KR1019950019145A KR19950019145A KR970003868A KR 970003868 A KR970003868 A KR 970003868A KR 1019950019145 A KR1019950019145 A KR 1019950019145A KR 19950019145 A KR19950019145 A KR 19950019145A KR 970003868 A KR970003868 A KR 970003868A
Authority
KR
South Korea
Prior art keywords
forming
flash memory
photoresist pattern
memory device
annealing
Prior art date
Application number
KR1019950019145A
Other languages
Korean (ko)
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019145A priority Critical patent/KR970003868A/en
Publication of KR970003868A publication Critical patent/KR970003868A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자 제조 방법.Semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 플래쉬 메모리 소자 제조 방법에 따르면 포토레지스트 패턴을 여러번 형성하고 제거하는 단계로 공정이 복잡하고 게이트 전극과 반도체 기판에 손상을 입히므로 소자의 수율이 떨어진다는 문제점을 해결하고자 함.According to a conventional flash memory device manufacturing method, a process of forming and removing a photoresist pattern several times is complicated, and the gate electrode and the semiconductor substrate are damaged, and thus the yield of the device is reduced.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

포토레지스트 패턴을 형성하는 공정을 줄이는 액상 절연막을 이용하여 이온주입을 실시하므로써 공정을 보다 간단히 하고 양호한 플래쉬 메모리 소자를 제조하고자 함.The ion implantation is performed using a liquid insulating film that reduces the process of forming a photoresist pattern, thereby simplifying the process and manufacturing a good flash memory device.

4. 발명의 주요한 용도4. Main uses of the invention

플래쉬 메모리 소자를 제조하는데 주로 이용됨.Mainly used to manufacture flash memory devices.

Description

플래쉬 메모리 소자 제조 방법Flash memory device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 플래쉬 메모리 소자 제조 방법에 따른 공정도.2A to 2E are process drawings according to the flash memory device manufacturing method of the present invention.

Claims (2)

플래쉬 메모리 소자를 제조하는 방법에 있어서, 반도체 기판에 게이트 산화막, 플로팅 게이트용 폴리실리콘, 산화막-질화막-산화막층 및 제어 게이트용 폴리실리콘을 차레로 증착하는 단계와, 게이트 전극을 형성하기 위한 제1포토레지스트를 패턴을 형성하는 단계와, 상기 제1포토레지스트 패턴을 식각 배리어로 이용하여 상기 제어 게이트용 폴리실리콘, 상기 산화막-질화막-산화막층, 상기 플로팅 게이트용 폴리실리콘 및 상기 게이트 산화막을 식각하여 적층형 게이트 전극을 형성하는 단계와, 상기 제1포토레지스트 패턴을 제거하고 소스/드레인영역 형성을 위한 이온 주입을 실시하는 단계와, 소스 영역이 오픈된 제2포토레지스트 패턴을 형성하고 소스 영역의 하부에 저도핑 소스 영역을 형성하기 위한 이온주입을 실시하는 단계와, 제2포토레지스트 패턴이 형성되지 않은 영역에 액상 절연막을 증착하는 단계 및 상기 제2포토레지스트 패턴을 제거하고 상기 드레인 영역에 주입된 이온과 반대 타입의 이온주입을 실시하고 어닐링시키는 단계를 포함하여 이루어진 플래쉬 메모리 소자 제조 방법.A method of manufacturing a flash memory device, comprising: sequentially depositing a gate oxide film, a floating gate polysilicon, an oxide-nitride-oxide layer, and a control gate polysilicon on a semiconductor substrate, and forming a gate electrode; Forming a photoresist pattern, etching the control gate polysilicon, the oxide film-nitride-oxide layer, the floating gate polysilicon, and the gate oxide film by using the first photoresist pattern as an etching barrier. Forming a stacked gate electrode, removing the first photoresist pattern and performing ion implantation to form a source / drain region, forming a second photoresist pattern with an open source region, and forming a lower portion of the source region Ion implantation to form a low doped source region in the second photoresist; Depositing a liquid insulating film in a region where no pattern is formed, and removing the second photoresist pattern, and performing annealing and annealing of ions implanted into the drain region, and annealing the flash memory device. Manufacturing method. 제1항에 있어서, 상기 어닐링 단계 후에 상기 액상절연막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.The method of claim 1, further comprising removing the liquid insulating film after the annealing step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019145A 1995-06-30 1995-06-30 Flash memory device manufacturing method KR970003868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019145A KR970003868A (en) 1995-06-30 1995-06-30 Flash memory device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019145A KR970003868A (en) 1995-06-30 1995-06-30 Flash memory device manufacturing method

Publications (1)

Publication Number Publication Date
KR970003868A true KR970003868A (en) 1997-01-29

Family

ID=66526345

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950019145A KR970003868A (en) 1995-06-30 1995-06-30 Flash memory device manufacturing method

Country Status (1)

Country Link
KR (1) KR970003868A (en)

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