KR970030808A - Flash memory device manufacturing method - Google Patents

Flash memory device manufacturing method Download PDF

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Publication number
KR970030808A
KR970030808A KR1019950043615A KR19950043615A KR970030808A KR 970030808 A KR970030808 A KR 970030808A KR 1019950043615 A KR1019950043615 A KR 1019950043615A KR 19950043615 A KR19950043615 A KR 19950043615A KR 970030808 A KR970030808 A KR 970030808A
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KR
South Korea
Prior art keywords
layer
forming
gate
device isolation
oxide layer
Prior art date
Application number
KR1019950043615A
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Korean (ko)
Inventor
황준
Original Assignee
김주용
현대전자산업주식회사
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Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019950043615A priority Critical patent/KR970030808A/en
Publication of KR970030808A publication Critical patent/KR970030808A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 기판(1)상에 소자 분리층(2)을 형성한 후, 게이트 산화층(3)과 제1폴리실리콘층(4)이 적층된 구조의 게이트 패턴을 형성하고, 이온 주입 공정으로 소스／드레인 영역(n+)을 형성하는 제1단계; 전체구조 표면을 따라 터널 산화층(5)을 형성한 후, 상기 게이트 패턴의 측벽 부위에 제2폴리실리콘층 스페이서(6)를 형성하는 제2단계; 상기 소자 분리층과 상기 제1폴리실리콘층의 상부 표면이 노출되도록 상기 터널 산화층을 패터닝한 후, 상기 제1폴리 실리콘층 및 제2폴리실리콘층 스페이서와 함께 플로팅 게이트가 되며, 캐패시티브 커플링 율을 향상시키기 위하여 상기 소자 분리층과 일부 중첩되는 제3폴리실리콘층(7) 패턴을 형성하는 제3단계; 및 전체구조 표면을 따라 절연층(8)을 형성한 후, 제어 게이트(9)를 형성하는 제4단계를 포함하는 것을 특징으로 하는 플래쉬 메모리 소자 제조방법에 관한 것으로, 커패시티브-커플링율을 증대시켜 집적도를 향상시킬 수 있도록 한 것이다.According to the present invention, after the device isolation layer 2 is formed on the substrate 1, a gate pattern having a structure in which the gate oxide layer 3 and the first polysilicon layer 4 are stacked is formed, and a source is formed by an ion implantation process. / A first step of forming the drain region n + ; A second step of forming a second polysilicon layer spacer 6 on the sidewall portion of the gate pattern after forming the tunnel oxide layer 5 along the entire structure surface; After the tunnel oxide layer is patterned to expose the upper surface of the device isolation layer and the first polysilicon layer, the tunnel oxide layer is a floating gate together with the first polysilicon layer and the second polysilicon layer spacer. Forming a third polysilicon layer (7) pattern partially overlapping the device isolation layer to improve the rate; And a fourth step of forming the control gate (9) after forming the insulating layer (8) along the entire structure surface, wherein the capacitive coupling rate is reduced. It is to increase the degree of integration.

Description

플래쉬 메모리 소자 제조 방법Flash memory device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도 내지 제1d도는 본 발명의 일실시예에 따른 플래쉬 메모리 소자의 제조 과정도.1A to 1D are diagrams illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

Claims (6)

기판 상에 소자 분리층을 형성한 후, 게이트 산화층과 제1폴리실리콘층이 적층된 구조의 게이트 패턴을 형성하고, 이온 주입 공정으로 소스／드레인 영역을 형성하는 제1단계; 전체구조 표면을 따라 터널 산화층을 형성한 후, 상기 게이트 패턴의 측벽 부위에 제2폴리실리콘층 스페이서를 형성하는 제2단계; 상기 소자 분리층과 상기 제1폴리실리콘층의 상부 표면이 노출되도록 상기 터널 산화층을 패터닝한 후, 상기 제1폴리 실리콘층 및 제2폴리실리콘층 스페이서와 함께 플로팅 게이트가 되며, 캐패시티브 커플링 율을 향상시키기 위하여 상기 소자 분리층과 일부 중첩되는 제3폴리실리콘층 패턴을 형성하는 제3단계; 및 전체구조 표면을 따라 절연층을 형성한 후, 제어 게이트를 형성하는 제4단계를 포함하는 것을 특징으로 하는 플래쉬 메모리 소자 제조방법.Forming a device isolation layer on the substrate, forming a gate pattern having a structure in which a gate oxide layer and a first polysilicon layer are stacked, and forming a source / drain region by an ion implantation process; A second step of forming a second polysilicon layer spacer on a sidewall of the gate pattern after forming a tunnel oxide layer along the entire structure surface; After the tunnel oxide layer is patterned to expose the upper surface of the device isolation layer and the first polysilicon layer, the gate oxide layer is a floating gate together with the first polysilicon layer and the second polysilicon layer spacer. Forming a third polysilicon layer pattern partially overlapping the device isolation layer to improve a rate; And forming a control gate after forming an insulating layer along the entire surface of the structure, and forming a control gate. 제1항에 있어서, 상기 제1단계는 상기 게이트 패턴의 측벽과 상기 소자 분리층의 에지 간 이격 거리를 가능한 줄여 수행되는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.The method of claim 1, wherein the first step is performed to reduce the distance between the sidewall of the gate pattern and the edge of the device isolation layer as much as possible. 제2항에 있어서, 상기 게이트 패턴의 측벽과 상기 소자 분리층의 에지 간 이격 거리는 0.1 내지 0.5㎛인 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.The method of claim 2, wherein the separation distance between the sidewall of the gate pattern and the edge of the device isolation layer is 0.1 μm to 0.5 μm. 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 터널 산화층은 옥시나이트라이드층인 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.4. The method of claim 1, wherein the tunnel oxide layer is an oxynitride layer. 제4항에 있어서, 상기 옥시나이트라이드층은 50 내지 100Å 형성되는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.5. The method of claim 4, wherein the oxynitride layer is formed in a range of 50 to 100 microseconds. 제4항에 있어서; 상기 터널 산화층은 N+영역외에도 필드산화층의 에지부위와 중첩되도록 형성하는 것을 특징으로 하는 플래쉬 메모리 소자 제조 방법.The method of claim 4; The tunnel oxide layer may be formed to overlap with the edge portion of the field oxide layer in addition to the N + region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950043615A 1995-11-24 1995-11-24 Flash memory device manufacturing method KR970030808A (en)

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KR1019950043615A KR970030808A (en) 1995-11-24 1995-11-24 Flash memory device manufacturing method

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Application Number Priority Date Filing Date Title
KR1019950043615A KR970030808A (en) 1995-11-24 1995-11-24 Flash memory device manufacturing method

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KR970030808A true KR970030808A (en) 1997-06-26

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