KR960019754A - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Manufacturing method of nonvolatile semiconductor memory device Download PDF

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Publication number
KR960019754A
KR960019754A KR1019940030882A KR19940030882A KR960019754A KR 960019754 A KR960019754 A KR 960019754A KR 1019940030882 A KR1019940030882 A KR 1019940030882A KR 19940030882 A KR19940030882 A KR 19940030882A KR 960019754 A KR960019754 A KR 960019754A
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KR
South Korea
Prior art keywords
forming
buried
oxide film
layer
region
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Application number
KR1019940030882A
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Korean (ko)
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KR0151186B1 (en
Inventor
임민규
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문정환
금성일렉트론 주식회사
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Priority to KR1019940030882A priority Critical patent/KR0151186B1/en
Publication of KR960019754A publication Critical patent/KR960019754A/en
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Publication of KR0151186B1 publication Critical patent/KR0151186B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 불휘발성 반도체 메모리장치의 제조방법에 관한 것으로, 레이아웃상와 면적을 감소시키면서 플로팅게이트와 매몰 n+영역이 접촉하는 표면적을 증가시켜 프로그래밍 효율을 증대시킬 수 있도록 한 것이다. 본 발명은 반도체기판 표면부위의 소정영역에 매몰 n+층을 형성하는 공정과, 상기 매몰 n+층 상부에 산화막을 형성하는 공정, 상기 산화막의 터널영역에 해당하는 부분을 선택적으로 제거하고 이에 따라 노출되는 상기 매몰 n+층을 식각하는 공정, 상기 식각된 부분에 n형 불순물의 이온주입을 실시하는 공정, 상기 식각에 의해 노출된 매몰 n+영역상에 터널 산화막을 형성하는 공정, 상기 터널 산화막을 포함한 기판의 소정영역상에 플로팅게이트를 형성하는 공정, 상기 플로팅게이트 전표면에 층간절연막을 형성하는 공정, 및 상기 층간절연막 전면에 컨트롤게이트를 형성하는 공정을 포함하여 이루어지는 불휘발성 반도체 메모리장치의 제조방법을 제공함으로써 EEPROM의 프로그래밍 효율을 향상시키며, 단위셀 면적을 감소시킬 수 있도록 한다.The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and to increase programming efficiency by increasing the surface area of the floating gate and the buried n + region while reducing the layout and area. According to the present invention, a process of forming a buried n + layer in a predetermined region on a surface of a semiconductor substrate, a process of forming an oxide film on the buried n + layer, and selectively removing a portion corresponding to a tunnel region of the oxide film Etching the exposed buried n + layer, performing ion implantation of n-type impurities in the etched portion, forming a tunnel oxide film on the buried n + region exposed by the etching, the tunnel oxide film Forming a floating gate on a predetermined region of the substrate, forming an interlayer insulating film on the entire surface of the floating gate, and forming a control gate on the entire surface of the interlayer insulating film. Providing a manufacturing method improves the programming efficiency of the EEPROM and reduces the unit cell area.

Description

불휘발성 반도체 메모리장치의 제조방법Manufacturing method of nonvolatile semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 FLOTOX형 EEPROM셀 제조방법을 도시한 공정순서도.3 is a process flowchart showing a FLOTOX type EEPROM cell manufacturing method according to the present invention.

Claims (2)

반도체기판 표면부위의 소정영역에 매몰 n+층 상부에 산화막을 형성하는 공정, 상기 매몰 n+층 상부에 산화막을 형성하는 공정, 상기 산화막의 터널영역에 해당하는 부분을 선택적으로 제거하고 이에 따라 노출되는 상기 매몰 n+층을 식각하는 공정, 상기 식각된 부분에 n형 불순물의 이온주입을 실시하는 공정, 상기 식각에 의해 노출된 매몰 n+영역상에 터널 산화막을 형성하는 공정, 상기 터널 산화막을 포함한 기판의 소정영역상에 플로팅게이트를 형성하는 공정, 상기 플로팅게이트 전표면에 층간절연막을 형성하는 공정, 및 상기 층간절연막 전면에 컨트롤게이트를 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 불휘발성 반도체 메모리장치의 제조방법.Forming an oxide film on the buried n + layer in a predetermined region of the surface of the semiconductor substrate, forming an oxide film on the buried n + layer, selectively removing a portion corresponding to the tunnel region of the oxide film and exposing the oxide film Etching the buried n + layer, performing ion implantation of n-type impurities into the etched portion, forming a tunnel oxide film on the buried n + region exposed by the etching, and removing the tunnel oxide film. Forming a floating gate on a predetermined region of the substrate, a step of forming an interlayer insulating film on the entire surface of the floating gate, and a step of forming a control gate on the entire surface of the interlayer insulating film. Method of manufacturing a memory device. 제1항에 있어서, 상기 매몰 n+층의 식각깊이는 매몰 n+층의 전체두께를 초과하지 않는 범위내로 제한하여 식각을 행하는 것을 특징으로 하는 불휘발성 반도체 메모리장치의 제조방법.The method of manufacturing the buried n + layer of the etching depth is buried n + nonvolatile, characterized in that performing the etching by limiting the range which does not exceed the overall thickness of the layer A semiconductor memory device according to claim 1. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940030882A 1994-11-23 1994-11-23 Method of manufacturing non-volatile semiconductor memory device KR0151186B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940030882A KR0151186B1 (en) 1994-11-23 1994-11-23 Method of manufacturing non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940030882A KR0151186B1 (en) 1994-11-23 1994-11-23 Method of manufacturing non-volatile semiconductor memory device

Publications (2)

Publication Number Publication Date
KR960019754A true KR960019754A (en) 1996-06-17
KR0151186B1 KR0151186B1 (en) 1998-10-01

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Application Number Title Priority Date Filing Date
KR1019940030882A KR0151186B1 (en) 1994-11-23 1994-11-23 Method of manufacturing non-volatile semiconductor memory device

Country Status (1)

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KR (1) KR0151186B1 (en)

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Publication number Publication date
KR0151186B1 (en) 1998-10-01

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