KR970017973A - Soi에 다수의 마이크로일렉트로닉 회로를 제조하기 위한 방법 - Google Patents

Soi에 다수의 마이크로일렉트로닉 회로를 제조하기 위한 방법 Download PDF

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KR970017973A
KR970017973A KR1019960041004A KR19960041004A KR970017973A KR 970017973 A KR970017973 A KR 970017973A KR 1019960041004 A KR1019960041004 A KR 1019960041004A KR 19960041004 A KR19960041004 A KR 19960041004A KR 970017973 A KR970017973 A KR 970017973A
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implantation
well
doped
polysilicon
layer
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KR1019960041004A
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KR100416843B1 (ko
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칼하인츠 뮐러
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로더리히 네테부쉬; 롤프 옴케
지멘스 악티엔게젤샤프트
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

본 발명은 표준화된 프로세스를 통해 예를 들어 n-CMOS- 또는 p-CMOS-프랜지스터, NPN-트랜지스터 또는 PNP-트랜지스터가 제조될 수 있는, SOI에 다수의 마이크로일렉트로닉 회로를 제조하기 위한 방법에 관한 것이다. 이를 위해 실시되는 주입에 의한 적응만이 필요하다.
＊ 선택도 제7도

Description

SOI에 다수의 마이크로일렉트로닉 회로를 제조하기 위한 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제7도는 본 발명에 따른 방법으로 만들어진 n-CMOS-프랜지스터의 단면도.

Claims (9)

  1. 절연 재료에 다수의 활성 영역(1)이 정해지는 단계, 이 활성 영역(1)에 만들어지는 구조체에 따라 n-웰 또는 p-웰(2)이 주입에 의해 형성되는 단계, 게이트 산화물(3)이 만들어져 상기 활성 영역(1)에서 구조화되는 단계, 제1의 폴리실리콘층(4)이 디포짓되는 단계, 만들어지는 구조체에 따라 p-또는n-주입이 실시되고 나중의 온도처리로 상기 웰(2)의 그 아래 있는 2개의 영역(18a)이 도핑되는 단계, 산화물층(7)이 디포짓되는 단계, 이 산화물층(7)과 그 아래 실리콘층(4)이 상기 활성 영역(8)을 정하기 위해 에칭되는 단계, 산화물층이 디포짓되고 이것으로부터 상기 활성 영역(8)의 에칭된 폴리실리콘 구조체에서 스페이서(9)가 에칭되는 단계, 제2의 폴리실리콘층(12)이 디포짓되는 단계, 만들어지는 구조체에 따라 n-또는 p-주입이 실시되는 단계, 상기 제2의 폴리실리콘층(12)이 구조화되고 산화 코팅이 제공되는 단계, 상기 만들어진 에지에서 스페이서(13)가 에칭되는 단계, 온도 처리로 상기 주입된 도핑 물질이 폴리실리콘(4, 12)으로부터 웰영역으로 확산되는 단계, 노출된 산화층이 적당한 금속의 제공에 의해 규소화되는 단계, 및 금속 접점(15)이 만들어지는 단계를 포함하는 SOI에 다수의 마이크로일렉트로닉 회로, 특히 CMOS-트랜지스터 및/또는 바이폴라 트랜지스터의 제조 방법.
  2. 제1항에 있어서, n-CMOS-구조체의 제조를 위해 먼저 p-웰이 주입에 의해 형성되고, 이 웰의 외측영역(18a)은 폴리실리콘층(4)의 도핑과 경화를 통해 n+도핑되고 이어서 양측의 n-도핑이 실시되는 것을 특징으로 하는 방법.
  3. 제1항에 있어서, p-CMOS-구조체의 제조를 위해 먼저 n-웰(2)이 주입에 의해 형성되고, 제1폴리실리콘층(4)이 p+도핑되고 이어서 상기 제2의 폴리실리콘층(12)의 양측의 p-도핑이 실시되는 것을 특징으로 하는 방법.
  4. 제1항에 있어서, NPN-트랜지스터의 제조를 위해 먼저 먼저 n-웰(2)이 주입에 의해 형성되고, 제1폴리실리콘층(4)이 n+도핑되고 이어서 베이스의 형성을 위해 한측의 p-도핑이 실시되는 것을 특징으로 하는 방법.
  5. 제1항에 있어서, PNP-트랜지스터의 제조를 위해 먼저 n-웰(2)이 주입에 의해 형성되고, 제1폴리실리콘층(4)이 p+도핑되고 이어서 베이스의 형성을 위해 한측의 n-도핑이 실시되는 것을 특징으로 하는 방법.
  6. 전술항 항 중 어느 한 항에 있어서, 다수의 동일한 구조체가 만들어지는 것을 특징으로 하는 방법.
  7. 제4항 내지 제6항 중 어느 한 항에 있어서, 트랜지스터 제조시에 베이스 폭이 2개측의 스페이서(9)를 통해 조절되는 것을 특징으로 하는 방법.
  8. 전술한 항 중 어느 한 항에 있어서, 이 폴리실리콘의 접촉이 접촉호울을 통해 이루어지는 것을 특징으로 하는 방법.
  9. 전술한 항 중 어느 한 항에 있어서, 상기 웰 영역이 단일한 경화프로세스를 통해 마지막의 주입 단계 후에 도핑되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960041004A 1995-09-28 1996-09-20 Soi에다수의마이크로일렉트로닉회로를제조하기위한방법 KR100416843B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19536249A DE19536249A1 (de) 1995-09-28 1995-09-28 Verfahren zur Herstellung einer Vielzahl von mikroelektronischen Schaltungen auf SOI
DE19536249.7 1995-09-28

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KR970017973A true KR970017973A (ko) 1997-04-30
KR100416843B1 KR100416843B1 (ko) 2004-05-14

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US (1) US5733803A (ko)
EP (1) EP0766305B1 (ko)
JP (1) JP3479191B2 (ko)
KR (1) KR100416843B1 (ko)
DE (2) DE19536249A1 (ko)
TW (1) TW324111B (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08255907A (ja) * 1995-01-18 1996-10-01 Canon Inc 絶縁ゲート型トランジスタ及びその製造方法
DE19758339C2 (de) * 1997-12-22 2003-09-25 X Fab Semiconductor Foundries Integrationsfähiger vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
US6368960B1 (en) * 1998-07-10 2002-04-09 Sharp Laboratories Of America, Inc. Double sidewall raised silicided source/drain CMOS transistor

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4276688A (en) * 1980-01-21 1981-07-07 Rca Corporation Method for forming buried contact complementary MOS devices
US4677735A (en) * 1984-05-24 1987-07-07 Texas Instruments Incorporated Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4837176A (en) * 1987-01-30 1989-06-06 Motorola Inc. Integrated circuit structures having polycrystalline electrode contacts and process
US5262344A (en) * 1990-04-27 1993-11-16 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
US5389561A (en) * 1991-12-13 1995-02-14 Sony Corporation Method for making SOI type bipolar transistor
US5164326A (en) * 1992-03-30 1992-11-17 Motorola, Inc. Complementary bipolar and CMOS on SOI
JPH05304164A (ja) * 1992-04-28 1993-11-16 Toshiba Corp 半導体装置
US5273915A (en) * 1992-10-05 1993-12-28 Motorola, Inc. Method for fabricating bipolar junction and MOS transistors on SOI
US5395775A (en) * 1993-07-02 1995-03-07 Siemens Aktiengesellschaft Method for manufacturing lateral bipolar transistors
US5545579A (en) * 1995-04-04 1996-08-13 Taiwan Semiconductor Manufacturing Company Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains

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Publication number Publication date
DE59611208D1 (de) 2005-04-21
EP0766305A3 (de) 1999-11-17
JP3479191B2 (ja) 2003-12-15
KR100416843B1 (ko) 2004-05-14
JPH09134971A (ja) 1997-05-20
DE19536249A1 (de) 1997-04-10
EP0766305B1 (de) 2005-03-16
US5733803A (en) 1998-03-31
EP0766305A2 (de) 1997-04-02
TW324111B (en) 1998-01-01

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