KR970008416A - 선택적 구리 증착방법 - Google Patents

선택적 구리 증착방법 Download PDF

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Publication number
KR970008416A
KR970008416A KR1019950021856A KR19950021856A KR970008416A KR 970008416 A KR970008416 A KR 970008416A KR 1019950021856 A KR1019950021856 A KR 1019950021856A KR 19950021856 A KR19950021856 A KR 19950021856A KR 970008416 A KR970008416 A KR 970008416A
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South Korea
Prior art keywords
copper
barrier metal
metal pattern
deposition method
cathode
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KR1019950021856A
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English (en)
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KR0157889B1 (ko
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김재정
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문정환
Lg 반도체 주식회사
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Priority to KR1019950021856A priority Critical patent/KR0157889B1/ko
Priority to JP8000925A priority patent/JP2821869B2/ja
Publication of KR970008416A publication Critical patent/KR970008416A/ko
Priority to US08/887,652 priority patent/US5985125A/en
Application granted granted Critical
Publication of KR0157889B1 publication Critical patent/KR0157889B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

본 발명은 선택적(selective) 구리 증착방법에 관한 것으로, 웨이퍼 상에 장벽금속 패턴을 형성하는 공정 및; 전기화학증착법에 의해 상기 장벽금속 패턴 상에 구리를 증착하는 공정을 구비하여 소자제조를 완료함으로써, 1) 증착되는 구리막질내에 탄소가 포함되지 않아 저항치가 1.7μΩ㎝인 순수구리를 얻을 수 있으며, 2) 먼저 웨이퍼 상에 장벽금속 패턴을 형성한 뒤, 상기 패턴 상에만 선택적으로 구리를 증착하므로 구리막의 식각 공정이 따로 필요하지 않게 되어 공정단순화를가할 수 있을 뿐 아니라 식각 공정시 야기되던 공정 상의 어려움을 제거할 수 있게 되고, 또한 3) 전해액에 HF를 첨가할경우, 세척(cleaning) 공정 없이 바로 선택적으로 구리를 증착할 수 있어 공정을 더욱 단순화할 수 있게 된다.

Description

선택적 구리 증착방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2(가)도 내지 제2(라)도는 본 발명으로서, 선택적 구리 증착법에 의한 반도체 소자 형성방법을 도시한 공정수순도.

Claims (7)

  1. 웨이퍼 상에 장벽금속 패턴을 형성하는 공정 및; 전기화학증착법에 의해 상기 장벽금속 패턴 상에 구리를증착하는 공정을 구비하여 형성되는 것을 특징으로 하는 선택적 구리 증착방법.
  2. 제1항에 있어서, 전기화학증착법으로 상기 장벽금속 패턴 상에 구리를 증착하는 공정은 장벽금속 패턴이형성된 웨이퍼를 Cu를 포함한 전해액이 담긴 용액에 담근 후 이를 캐소드에 연결하는 공정 및; 상기 캐소드에는 (-)전하를, 구리판을 연결한 애노드에는 (+)전하를 인가하는 공정을 더 포함하여 상기 전해액에 용해되어 있는 구리가 선택적으로 장벽금속 패턴에 증착되도록 하는 것을 특징으로 하는 선택적 구리 증착방법.
  3. 제1항에 있어서, 상기 장벽금속 패턴은 TiN 또는 TiW 중 선택된 어느 하나로 형성하는 것을 특징으로 하는선택적 구리 증착방법.
  4. 제2항에 있어서, 상기 Cu를 포함한 전해액은 CuSO4+ H2SO4+ DI 워터로 형성하는 것을 특징으로 하는 선택적구리 증착방법.
  5. 제2항 또는 제4항에 있어서, 상기 Cu를 포함한 전해액은 HF를 더 포함하여 형성하는 것을 특징으로 하는선택적 구리 증착방법.
  6. 제2항 또는 제4항에 있어서, 상기 전해액 중 CuSO4는 그 농도를 10㏖ 이하로 형성하는 것을 특징으로 하는선택적 구리 증착방법.
  7. 제2항에 있어서, 상기 캐소드에는 레퍼런스 전극에 대해 -10V 이하의 음전하를 인가하는 것을 특징으로 하는 선택적 구리 증착방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950021856A 1995-07-24 1995-07-24 선택적 구리 증착방법 KR0157889B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950021856A KR0157889B1 (ko) 1995-07-24 1995-07-24 선택적 구리 증착방법
JP8000925A JP2821869B2 (ja) 1995-07-24 1996-01-08 半導体素子の選択的銅蒸着方法
US08/887,652 US5985125A (en) 1995-07-24 1997-07-03 Selective copper deposition method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950021856A KR0157889B1 (ko) 1995-07-24 1995-07-24 선택적 구리 증착방법

Publications (2)

Publication Number Publication Date
KR970008416A true KR970008416A (ko) 1997-02-24
KR0157889B1 KR0157889B1 (ko) 1999-02-01

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US (1) US5985125A (ko)
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Publication number Priority date Publication date Assignee Title
US6627539B1 (en) * 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6180526B1 (en) * 1999-09-17 2001-01-30 Industrial Technology Research Institute Method for improving conformity of a conductive layer in a semiconductor device
US6344125B1 (en) * 2000-04-06 2002-02-05 International Business Machines Corporation Pattern-sensitive electrolytic metal plating
US6472312B2 (en) * 2001-01-16 2002-10-29 Taiwan Semiconductor Manufacturing Co., Ltd Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation
US7368045B2 (en) * 2005-01-27 2008-05-06 International Business Machines Corporation Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow
JP4471004B2 (ja) * 2008-01-23 2010-06-02 セイコーエプソン株式会社 接合体の形成方法
JP4471003B2 (ja) * 2008-01-23 2010-06-02 セイコーエプソン株式会社 接合体の形成方法
JP4471002B2 (ja) * 2008-01-23 2010-06-02 セイコーエプソン株式会社 接合体の形成方法
US11031517B2 (en) 2017-11-08 2021-06-08 Korea Institute Of Science And Technology Method of manufacturing light transmission type compound thin film, compound thin film manufactured therefrom, and solar cell including the same
WO2019093558A1 (ko) * 2017-11-08 2019-05-16 한국과학기술연구원 투광형 화합물 박막 제조 방법, 이로부터 제조된 화합물 박막 및 이러한 화합물 박막을 포함하는 태양 전지

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE340392B (ko) * 1969-05-27 1971-11-15 Asea Ab
JPS5321048A (en) * 1976-08-10 1978-02-27 Nippon Electric Co Constant current density plating device
US4169018A (en) * 1978-01-16 1979-09-25 Gould Inc. Process for electroforming copper foil
JPH03244126A (ja) * 1990-02-22 1991-10-30 Toshiba Corp 半導体装置の製造方法
KR940008327B1 (ko) * 1991-10-10 1994-09-12 삼성전자 주식회사 반도체 패키지 및 그 실장방법
JPH05109714A (ja) * 1991-10-15 1993-04-30 Nec Corp 半導体装置の製造方法
US5225034A (en) * 1992-06-04 1993-07-06 Micron Technology, Inc. Method of chemical mechanical polishing predominantly copper containing metal layers in semiconductor processing
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5478773A (en) * 1994-04-28 1995-12-26 Motorola, Inc. Method of making an electronic device having an integrated inductor

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Publication number Publication date
US5985125A (en) 1999-11-16
KR0157889B1 (ko) 1999-02-01
JPH0936064A (ja) 1997-02-07
JP2821869B2 (ja) 1998-11-05

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