KR970003498A - Contact formation method of semiconductor device - Google Patents

Contact formation method of semiconductor device Download PDF

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Publication number
KR970003498A
KR970003498A KR1019950017581A KR19950017581A KR970003498A KR 970003498 A KR970003498 A KR 970003498A KR 1019950017581 A KR1019950017581 A KR 1019950017581A KR 19950017581 A KR19950017581 A KR 19950017581A KR 970003498 A KR970003498 A KR 970003498A
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KR
South Korea
Prior art keywords
contact hole
film
forming
nitride film
contact
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KR1019950017581A
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Korean (ko)
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KR100192170B1 (en
Inventor
박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019950017581A priority Critical patent/KR100192170B1/en
Publication of KR970003498A publication Critical patent/KR970003498A/en
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Publication of KR100192170B1 publication Critical patent/KR100192170B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택 형성방법에 관한 것으로, 보다 구체적으로는 콘택 형성공정시, 접합 영역 또는 게이트 전극상에 선택적으로 형성된 실리사이드막이 콘택홀을 위한 식각 공정에서 언더 컷에 의한 손실을 방지 및 미세한 콘택홀을 형성하여 금속 배선의 신뢰성을 향상시키고, 소자의 제조 수율을 향상시킬 수 있는 반도체 소자의 콘택 형성방법에 관한 것으로, 본 발명에서는 반도체 소자의 콘택 공정시 접합 영역의 접촉 저항 개선을 위한 실리사이드의 손실을 방지 및 미세한 콘택홀을 형성하기 위하여, 콘택홀 내벽에 스페이서를 제조하여 미세한 콘택홀을 형성할 수 있으며, 또한 실리사이드 상부의 제1질화막상에 소정의 이온 주입을 실시한 다음, 식각을 실시하여 등방성 식각에 의한 언더 컷 현상을 방지하고, 상부 배선 형성시 단선 또는 보이드를 방지할 수 있어 이후의 금속 배선 공정시 신뢰성 및 제조 수율을 향상시킨다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device. More specifically, a silicide film selectively formed on a junction region or a gate electrode during a contact forming process prevents and prevents a loss due to undercut in an etching process for a contact hole. The present invention relates to a method for forming a contact of a semiconductor device capable of forming a contact hole to improve the reliability of metal wiring and to improve the manufacturing yield of the device. The present invention relates to a silicide for improving contact resistance of a junction region during a contact process of a semiconductor device. In order to prevent loss and to form a fine contact hole, a spacer may be manufactured on the inner wall of the contact hole to form a fine contact hole, and a predetermined ion implantation may be performed on the first nitride layer on the silicide, followed by etching. This prevents undercut phenomenon caused by isotropic etching. The voids can be prevented to improve reliability and manufacturing yield in subsequent metallization processes.

Description

반도체 소자의 콘택 형성방법Contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (a) 내지 (e)는 본 발명에 따른 반도체 소자의 콘택 형성을 순차적으로 나타낸 도면.2 (a) to (e) sequentially show contact formation of a semiconductor device according to the present invention.

Claims (8)

능동 소자를 구비하여 비평탄화된 반도체 기판상의 전극 상부와 접합 영역 상부에 선택적으로 실리사이드막을 형성하는 단계; 상기 전체 구조 상부에 제1질화막, 제1TEOS막, BPSG막 및 제2질화막을 적층하는 단계; 상기 제2질화막 상부에 콘택홀을 형성하기 위한 마스크 패턴을 형성하고, 그의 형태로 하부의 제1TEOS막이 노출되도록 제1콘택홀을 형성하는 단계; 상기 전체 구조 상부에 제2TEOS막을 형성하고, 이방성식각하여 상기 제1콘택홀 내벽에 스페이서를 제조하는 단계; 상기 제조된 스페이서의 형태로 하부의 제1TEOS막을 식각하여 제1질화막의 일정 부분을 노출시키는 단계; 상기노출된 제1질화막 및 최상단의 제2질화막에 이온 주입 공정을 실시하는 단계; 상기 이온 주입된 제1질화막의 소정 부분과 상부의 제2질화막을 식각하여 콘택홀을 형성하는 단계; 및 금속 배선을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.Selectively forming a silicide film over the electrode and the junction region on the unplanarized semiconductor substrate with an active element; Stacking a first nitride film, a first TEOS film, a BPSG film, and a second nitride film on the entire structure; Forming a mask pattern for forming a contact hole on the second nitride film, and forming a first contact hole so that the lower first TEOS film is exposed in the form thereof; Forming a second TEOS film on the entire structure and anisotropically etching the second contact hole to manufacture a spacer on an inner wall of the first contact hole; Etching a lower first TEOS film in the form of the prepared spacers to expose a portion of the first nitride film; Performing an ion implantation process on the exposed first nitride film and the uppermost second nitride film; Etching a predetermined portion of the ion implanted first nitride film and an upper second nitride film to form a contact hole; And performing a metal wiring. 제1항에 있어서, 상기 이온 주입 원자는 Ar인 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the ion implantation atom is Ar. 제1항 또는 제2항에 있어서, 상기 이온 주입 원자는 20∼100KeV에너지 범위로, 농도는 1×1012내지 1×1018원자/㎠로 하여 이온 주입하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The semiconductor device of claim 1, wherein the ion implantation atoms are implanted with an ion implantation in an energy range of 20 to 100 KeV and a concentration of 1 × 10 12 to 1 × 10 18 atoms / cm 2. Way. 제1항에 있어서, 상기 이온 주입된 제1질화막 및 상단의 제2질화막을 식각하는 방법은 150 내지 180℃의 인산 용액을 이용하여 습식 식각하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the ion-implanted first nitride layer and the second nitride layer on the top are wet-etched using a phosphoric acid solution at 150 ° C. to 180 ° C. 3. 제1항에 있어서, 상기 제1질화막의 두께는 200 내지 800Å인 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the first nitride film has a thickness of 200 to 800 GPa. 제1항에 있어서, 상기 제1TEOS막은 1000 내지 3000Å인 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the first TEOS film is 1000 to 3000 microns. 제1항에 있어서, 상기 제2질화막의 두께는 200 내지 400Å인 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the second nitride film has a thickness of 200 to 400 GPa. 제1항에 있어서, 상기 제2TEOS막은 1000 내지 3000Å인 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the second TEOS film is 1000 to 3000 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017581A 1995-06-26 1995-06-26 Method for forming a contact of semiconductor device KR100192170B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950017581A KR100192170B1 (en) 1995-06-26 1995-06-26 Method for forming a contact of semiconductor device

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KR970003498A true KR970003498A (en) 1997-01-28
KR100192170B1 KR100192170B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100845718B1 (en) * 2002-12-20 2008-07-10 동부일렉트로닉스 주식회사 Method for manufacturing MOS transistor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990025132A (en) * 1997-09-10 1999-04-06 윤종용 Contact Forming Method of Semiconductor Device
KR100467021B1 (en) * 2002-08-20 2005-01-24 삼성전자주식회사 Contact structure of semiconductro device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100845718B1 (en) * 2002-12-20 2008-07-10 동부일렉트로닉스 주식회사 Method for manufacturing MOS transistor

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