KR0162143B1 - Method of contact hole formation in semiconductor device - Google Patents
Method of contact hole formation in semiconductor device Download PDFInfo
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- KR0162143B1 KR0162143B1 KR1019940039114A KR19940039114A KR0162143B1 KR 0162143 B1 KR0162143 B1 KR 0162143B1 KR 1019940039114 A KR1019940039114 A KR 1019940039114A KR 19940039114 A KR19940039114 A KR 19940039114A KR 0162143 B1 KR0162143 B1 KR 0162143B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로서, 시리콘 기판상에 소정 패턴의 게이트 산화막, 도핑된 폴리실리콘막, 실리사이드막을 순차적으로 적층 및 게이트 전극을 형성하는 단계와, 저농도 불순물 주입 단계와, 폴리실리콘막을 증착하고 이방성 식각하여 폴리실리콘막 스페이서를 형성하는 단계와, 고농도 불순물 주입 단계와, 전면에 절연막과 제2 폴리실리콘막을 형성하는 단계와, 상기 제2 폴리실리콘막과 상기 절연막을 소정의 패턴에 의하여 식각하는 단계와, 소자 전면에 이온을 주입하는 단계와, 상기 절연막을 식각정지층으로 하여 블랭킷 식각하는 단계 및 금속 배선을 이루는 단계를 구비하는 것을 특징으로 한다. 이와같은 본 발명은 실리콘기판과 게이트 전극이 동시에 노출되는 소정의 콘택홀 형성시, 접촉면적을 증대시킬 수 있어 소자의 제조수율과 스피드면을 개선하고 신뢰성을 향상시킬 수 있다.The present invention relates to a method for forming a contact hole in a semiconductor device, comprising: sequentially depositing a gate oxide film, a doped polysilicon film, and a silicide film on a silicon substrate and forming a gate electrode; Forming a polysilicon film spacer by depositing and anisotropically etching the polysilicon film, implanting a high concentration impurity, forming an insulating film and a second polysilicon film on the front surface, and preserving the second polysilicon film and the insulating film. Etching by a pattern, implanting ions into the entire surface of the device, blanket etching using the insulating layer as an etch stop layer, and forming metal wiring. As described above, the present invention can increase the contact area when forming a predetermined contact hole in which the silicon substrate and the gate electrode are simultaneously exposed, thereby improving the manufacturing yield and speed of the device and improving reliability.
Description
제1도는 종래의 반도체 소자의 콘택 홀 형성 방법을 나타내는 도.1 is a view showing a method for forming a contact hole in a conventional semiconductor device.
제1도 (a)는 종래의 반도체 소자의 콘택 홀의 평면도.1A is a plan view of a contact hole of a conventional semiconductor device.
제1도 (b)는 제1도 (a)의 A-A' 선에 대응하는 부분을 나타내는 것으로, 공정 단계를 순차적으로 보여주는 단면도.FIG. 1B is a cross-sectional view showing a portion corresponding to the line A-A 'of FIG. 1A and sequentially showing the process steps.
제2도는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 각 제조 공정에 있어서의 반도체 소자의 단면도.2 is a cross-sectional view of a semiconductor device in each manufacturing process for explaining a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 실리콘기판 2,12 : 게이트 산화막1,11 silicon substrate 2,12 gate oxide film
3,13 : 도핑된 폴리실리콘막 4,14 : 실리사이드막3,13 doped polysilicon film 4,14 silicide film
5 : 산화막 스페이서 6,16 : 불순물 확산 영역5 oxide film spacer 6,16 impurity diffusion region
7,17 : 절연막 8 : 콘택홀7,17 insulating film 8: contact hole
15 : 폴리실리콘막 스페이서 18 : 제2 폴리실리콘막15 polysilicon film spacer 18 second polysilicon film
19 : 요홈 20 : 금속 배선19: groove 20: metal wiring
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 폴리사이드 구조를 가지는 게이트 전극과 소정의 불순물이 도핑된 실리콘기판을 동시에 노출시키므로써 접촉면적을 증대시킬 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, a method for forming a contact hole in a semiconductor device capable of increasing a contact area by simultaneously exposing a gate electrode having a polyside structure and a silicon substrate doped with a predetermined impurity. Is about
일반적으로 소자의 집적도가 증가함에 따라 유효 채널의 폭이 0.5㎛ 이내인 미세한 소자를 형성함으로 인하여, 콘택홀 영역의 폭 또한 0.2㎛ 이내로 감소하게 되었다 이로 인하여 접촉 면적 또한 상대적으로 감소하여 소자의 신뢰성과 스피드면이 저하되게 되었다.In general, as the integration degree of the device increases, the width of the contact hole area is also reduced to within 0.2 μm by forming a fine device having an effective channel width of less than 0.5 μm. The speed surface was reduced.
종래의 반도체 소자의 콘택홀 형성 방법에 있어서, 제1도 (a) 및 제1도 (b)에 나타낸 바와 같이, 실리콘기판(1) 상에 소정 패턴의 게이트 산화막(2) 및 도핑된 폴리실리콘막(3)을 헝성한 다음, 불순물을 확산시켜 불순물 확산영역(6)을 형성하고, 전체구조의 상부에 절연막(7)을 증착시킨 후 산화막 스페이서(5)(제1도 (a)에 점선으로 표시되어 있음)를 형성하여 사진식각법으로 콘택홀(8)을 형성한다.In the conventional method for forming a contact hole in a semiconductor device, as shown in FIGS. 1A and 1B, a gate oxide film 2 and a doped polysilicon of a predetermined pattern are formed on a silicon substrate 1. After the film 3 is formed, the impurities are diffused to form the impurity diffusion region 6, and the insulating film 7 is deposited on the upper portion of the entire structure, followed by the dotted line on the oxide film spacer 5 (FIG. 1A). The contact hole 8 is formed by photolithography.
이때, 콘택홀(8)을 형성하기 위한 마스크가 오정렬(misalignment) 하게 되면, 불순물 확산 영역(6)의 노출 및 게이트 전극인 실리사이드막(4)의 노출 영역이 각각 변하게 되며, 심한 경우, 어느 한쪽으로 치우쳐 실리콘 기판과의 접속불량이 야기되는 문제점이 발생한다.At this time, when the mask for forming the contact hole 8 is misaligned, the exposure of the impurity diffusion region 6 and the exposure region of the silicide film 4 serving as the gate electrode are changed, respectively. In this case, a problem arises in that a poor connection with the silicon substrate is caused.
따라서, 본 발명의 목적은 상기 종래의 문제점을 해결하기 위하여 실리콘 기판에 요홈을 용이하게 형성하여 접촉면적을 증대시킬 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데에 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of easily forming grooves in a silicon substrate to increase the contact area in order to solve the above problems.
상기 목적을 달성하기 위하여, 본 발명은 반도체 소자의 콘택홀 형성 방법에 있어서 실리콘 기판상에 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 양측 소정부에 저농도 불순물 주입 단계와, 상기 전체 구조 상부에 제 1폴리실리콘막을 증착하고 이방성 식각하여 게이트 측벽 스페이서를 형성하는 단계와, 상기 게이트 측벽 양측에 고농도 불순물 주입하여 불순물 확산 영역을 형성하는 단계와, 전면에 절연막과 제 2폴리실리콘막을 형성하는 단계와, 상기 제 2폴리실리콘막과 상기 절연막을 소정의 패턴에 하여 식각하는 단계와, 소자 전면에 이온을 주입하는 단계와, 상기 절연막을 식각정지층으로 하여 블랭킷 식각하는 단계 및 금속 배선을 이루는 단계를 구비하는 것을 특징으로 한다In order to achieve the above object, the present invention provides a method for forming a contact hole in a semiconductor device, forming a gate electrode on a silicon substrate, implanting low concentration impurities into predetermined portions on both sides of the gate electrode, and Forming a gate sidewall spacer by depositing and anisotropically etching the first polysilicon film, forming a dopant diffusion region by implanting a high concentration of impurities into both sides of the gate sidewall, and forming an insulating film and a second polysilicon film on the front surface thereof; Etching the second polysilicon film and the insulating film in a predetermined pattern; implanting ions into the entire surface of the device; blanket etching the insulating film as an etch stop layer; and forming metal wirings. It is characterized by having
이하, 본 발명의 일실시예를 첨부 도면을 참고로하여 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 각 제조 공정에 있어서의 반도체 소자의 요부 단면도이다. 우선, 제2도 (a)에 도시된 바와 같이, 실리콘기판(11) 상에 소정의 두께를 가진 게이트산화막(12), 도핑된 폴리실리콘막(13), 및 실리사이드막(14)을 각각 적층하고, 사진식각에 의해 상기 도핑된 폴리실리콘막(13)과 실리사이드막(14)으로 구성된 게이트 전극을 형성한 다음, 핫 캐리어를 방지하기 위한 저농도 불순물을 주입한 후, 소정 두께의 폴리실리콘막을 증착한 후 이방성 식각에 의하여 스페이서(15)를 형성한다. 이때의 폴리실리콘막의 두께는 스페이서의 두께를 조절하는 변수이며, 상기 스페이서를 폴리실리콘으로 사용한 것은 추후, 금속 배선시 접촉 면적을 확보할 수 있기 때문이다. 그후, 고농도 불순물을 주입하고 어닐링하여 불순물 확산영역(16)을 형성하고, 상기 구성된 소자의 전면에 약 2,500 내지 3,500Å의 절연막(17)과 약 500 내지 1,000Å의 제2 폴리실리콘막(18)을 증착한다.2 is a cross-sectional view of principal parts of a semiconductor device in each manufacturing process for explaining a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 2A, a gate oxide film 12, a doped polysilicon film 13, and a silicide film 14 having a predetermined thickness are laminated on the silicon substrate 11, respectively. And forming a gate electrode composed of the doped polysilicon layer 13 and the silicide layer 14 by photolithography, injecting a low concentration impurity to prevent hot carriers, and then depositing a polysilicon layer having a predetermined thickness. After that, the spacer 15 is formed by anisotropic etching. The thickness of the polysilicon film at this time is a variable for controlling the thickness of the spacer, and the use of the spacer as the polysilicon is because the contact area can be secured during metal wiring later. Thereafter, a high concentration of impurities are implanted and annealed to form an impurity diffusion region 16, and an insulating film 17 of about 2,500 to 3,500 에 and a second polysilicon film 18 of about 500 to 1,000 Å are formed on the entire surface of the device. Deposit.
그런 다음, 소정의 사진식각 공정에 의해 제조된 마스크 패턴(도시되지 않음)을 이용하여 염소(Cl2) 가스 및 헬륨(He)가스를 이용하여 상기 제2 폴리실리콘막(18)을 식각하고, 제2도(b)에 나타낸 바와 같이; CF4, CHF3, Ar 등을 이용하여 상기 절연막(17)을 식각하므로써, 실리콘기판(11) 내의 불순물 확산영역(16), 폴리실리콘막 스페이서(15) 및 실리사이드막(14)을 노출시킨 다음, 수직방향으로 아르곤 원자를 30 내지 100KeV, 1×1013내지 1×1017원자/㎠의 조건으로 이온 주입한다.Then, the second polysilicon layer 18 is etched using chlorine (Cl 2 ) gas and helium (He) gas using a mask pattern (not shown) manufactured by a predetermined photolithography process. As shown in FIG. 2 (b); By etching the insulating film 17 using CF 4 , CHF 3 , Ar, or the like, the impurity diffusion region 16, the polysilicon film spacer 15, and the silicide film 14 in the silicon substrate 11 are exposed. In the vertical direction, argon atoms are implanted under the conditions of 30 to 100 KeV and 1 × 10 13 to 1 × 10 17 atoms / cm 2.
그후, 제2도 (c)에 도시된 바와 같이, 상기 절연막(17)을 식각정지층으로 사용하여 노출된 제 2 폴리실리콘막(18)과 폴리실리콘막 스페이서(15)와 실리콘기판(11)을 블랭킷 식각하여 실리콘기판 내에 요홈(19)을 형성한다. 그런 다음, 전체 구조의 상부에 소정 패턴의 금속 배선(20)을 형성한다 (제2도(d) 참고). 이때 사용되는 금속 배선으로는 도핑된 폴리실리콘을 사용하였다.Thereafter, as shown in FIG. 2 (c), the second polysilicon film 18, the polysilicon film spacer 15, and the silicon substrate 11 exposed using the insulating film 17 as an etch stop layer. Blanket etching to form grooves 19 in the silicon substrate. Then, the metal wiring 20 of a predetermined pattern is formed on the whole structure (refer to FIG. 2 (d)). In this case, doped polysilicon was used as the metal wiring.
이상과 같이 본 발명에 의하면, 실리콘기판과 게이트 전극이 동시에 노출되는 소정의 콘택홀 형성시, 접촉면적을 증대시킬 수 있어 소자의 제조수율과 스피드면을 개선하고 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, when forming a predetermined contact hole in which the silicon substrate and the gate electrode are simultaneously exposed, the contact area can be increased, thereby improving the manufacturing yield and speed of the device and improving reliability.
또한, 본 발명은 상기 실시예에 한정되는 깃은 아니다. 예를들면, 상기 실시예에서는 금속 배선막으로 도핑이 이루어진 폴리실리콘을 이용하였지만 그 막의 알루미늄 또는 알루미늄과 합금된 금속을 이용한 경우도 동일하게 적용할 수 있다.In addition, this invention is not a feather limited to the said Example. For example, in the above embodiment, polysilicon doped with a metal wiring film is used, but the same applies to the case of using aluminum or an alloy of aluminum with the film.
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KR1019940039114A KR0162143B1 (en) | 1994-12-30 | 1994-12-30 | Method of contact hole formation in semiconductor device |
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KR1019940039114A KR0162143B1 (en) | 1994-12-30 | 1994-12-30 | Method of contact hole formation in semiconductor device |
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KR0162143B1 true KR0162143B1 (en) | 1999-02-01 |
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