KR970003230B1 - 멀티포트 반도체 기억장치 - Google Patents

멀티포트 반도체 기억장치 Download PDF

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Publication number
KR970003230B1
KR970003230B1 KR1019930001825A KR930001825A KR970003230B1 KR 970003230 B1 KR970003230 B1 KR 970003230B1 KR 1019930001825 A KR1019930001825 A KR 1019930001825A KR 930001825 A KR930001825 A KR 930001825A KR 970003230 B1 KR970003230 B1 KR 970003230B1
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KR
South Korea
Prior art keywords
data
memory cell
memory
signal
sense amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019930001825A
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English (en)
Korean (ko)
Other versions
KR930018373A (ko
Inventor
고지 유루마
가주나리 이노우에
준코 마쯔모토
Original Assignee
미쓰비시 뎅끼 가부시끼가이샤
시기 모리야
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Publication date
Application filed by 미쓰비시 뎅끼 가부시끼가이샤, 시기 모리야 filed Critical 미쓰비시 뎅끼 가부시끼가이샤
Publication of KR930018373A publication Critical patent/KR930018373A/ko
Application granted granted Critical
Publication of KR970003230B1 publication Critical patent/KR970003230B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
KR1019930001825A 1992-02-13 1993-02-11 멀티포트 반도체 기억장치 Expired - Fee Related KR970003230B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-026881 1992-02-13
JP4026881A JPH05225774A (ja) 1992-02-13 1992-02-13 マルチポート半導体記憶装置

Publications (2)

Publication Number Publication Date
KR930018373A KR930018373A (ko) 1993-09-21
KR970003230B1 true KR970003230B1 (ko) 1997-03-15

Family

ID=12205627

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930001825A Expired - Fee Related KR970003230B1 (ko) 1992-02-13 1993-02-11 멀티포트 반도체 기억장치

Country Status (4)

Country Link
US (1) US5313431A (enExample)
JP (1) JPH05225774A (enExample)
KR (1) KR970003230B1 (enExample)
DE (1) DE4236453C2 (enExample)

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JPH06162784A (ja) * 1992-11-17 1994-06-10 Oki Micro Design Miyazaki:Kk 半導体集積回路装置
US5754478A (en) * 1993-04-20 1998-05-19 Micron Technology, Inc. Fast, low power, write scheme for memory circuits using pulsed off isolation device
US5506814A (en) * 1993-05-28 1996-04-09 Micron Technology, Inc. Video random access memory device and method implementing independent two WE nibble control
JPH0736778A (ja) * 1993-07-21 1995-02-07 Toshiba Corp 画像メモリ
JP3086769B2 (ja) * 1993-09-29 2000-09-11 株式会社東芝 マルチポートフィールドメモリ
US5678017A (en) * 1995-03-24 1997-10-14 Micron Technology, Inc. Automatic reloading of serial read operation pipeline on last bit transfers to serial access memory in split read transfer operations
US5523979A (en) * 1995-04-13 1996-06-04 Cirrus Logic, Inc. Semiconductor memory device for block access applications
US5553028A (en) * 1995-06-23 1996-09-03 Micron Technology, Inc. Single P-sense AMP circuit using depletion isolation devices
JP3351692B2 (ja) * 1995-09-12 2002-12-03 株式会社東芝 シンクロナス半導体メモリ装置
US5805931A (en) * 1996-02-09 1998-09-08 Micron Technology, Inc. Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5787041A (en) * 1996-10-01 1998-07-28 Hewlett-Packard Co. System and method for improving a random access memory (RAM)
JP3706212B2 (ja) * 1996-10-30 2005-10-12 沖電気工業株式会社 メモリ装置
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
JPH10334662A (ja) * 1997-05-29 1998-12-18 Nec Corp 半導体記憶装置
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
EP0954180B1 (en) * 1998-04-28 2006-02-08 Sanyo Electric Co., Ltd. Serial data transfer device
JP3248617B2 (ja) * 1998-07-14 2002-01-21 日本電気株式会社 半導体記憶装置
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) * 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6788614B2 (en) * 2001-06-14 2004-09-07 Micron Technology, Inc. Semiconductor memory with wordline timing
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
JP2006252624A (ja) * 2005-03-09 2006-09-21 Toshiba Corp 半導体記憶装置
KR100735612B1 (ko) * 2005-12-22 2007-07-04 삼성전자주식회사 멀티패쓰 억세스블 반도체 메모리 장치
KR100781983B1 (ko) * 2006-11-15 2007-12-06 삼성전자주식회사 체크 정보 제공기능을 가지는 멀티패쓰 억세스블 반도체메모리 장치
US7443751B2 (en) * 2006-12-22 2008-10-28 Qimonda North American Corp. Programmable sense amplifier multiplexer circuit with dynamic latching mode
KR100855587B1 (ko) 2007-01-17 2008-09-01 삼성전자주식회사 메일박스 영역을 가지는 멀티 패스 액세스블 반도체 메모리장치 및 그에 따른 메일박스 액세스 제어방법
JP5106513B2 (ja) * 2009-10-28 2012-12-26 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP2014067241A (ja) * 2012-09-26 2014-04-17 Fujitsu Semiconductor Ltd 半導体記憶装置及び電子装置
JP2016167331A (ja) * 2015-03-10 2016-09-15 株式会社東芝 半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2919166C2 (de) * 1978-05-12 1986-01-02 Nippon Electric Co., Ltd., Tokio/Tokyo Speichervorrichtung
US4897818A (en) * 1983-12-30 1990-01-30 Texas Instruments Incorporated Dual-port memory with inhibited random access during transfer cycles
US5170157A (en) * 1986-05-20 1992-12-08 Takatoshi Ishii Memory device for an image display apparatus having a serial port and independently operable data registers
KR960001106B1 (ko) * 1986-12-17 1996-01-18 가부시기가이샤 히다찌세이사꾸쇼 반도체 메모리
JP2880547B2 (ja) * 1990-01-19 1999-04-12 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
KR930018373A (ko) 1993-09-21
DE4236453C2 (de) 1994-11-03
JPH05225774A (ja) 1993-09-03
US5313431A (en) 1994-05-17
DE4236453A1 (enExample) 1993-08-19

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