KR960039123A - 플라즈마 성막방법 및 그 장치 - Google Patents

플라즈마 성막방법 및 그 장치 Download PDF

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KR960039123A
KR960039123A KR1019960010132A KR19960010132A KR960039123A KR 960039123 A KR960039123 A KR 960039123A KR 1019960010132 A KR1019960010132 A KR 1019960010132A KR 19960010132 A KR19960010132 A KR 19960010132A KR 960039123 A KR960039123 A KR 960039123A
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히데아키 아마노
겐이치 가타기리
마코토 도라구치
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이노우에 아키라
도쿄 일렉트론 가부시키가이샤
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Abstract

플라즈마 생성가스와 반응가스는 진공용기로 도입되고, 플라즈마 생성을 위한 마이크로파와 자계가 진공용기에 인가되며, 플라즈마는 ECR을 이용하여 생성되고, 예컨대 알루미늄배선상에 SiO2 또는 SiOF막이 형성된다. 막성막의 초기 위상에 있어서, 스테이지에 인가된 플라즈마 도입을 위한 무선주파수 전력의 레벨은 예컨대 미리 "0"으로 조정된다. 웨이퍼의 표면상의 자기 바이어스 전압이 그때 "0"이기 때문에, 예컨대 웨이퍼표면의 전위분포는 사실상 플라즈마의 전위분포에 의존한다. 평면방향에서 플라즈마의 전위차가 많아야 1볼트정도로 작기 때문에, 웨이퍼상에 미리 형성된 게이트 산화막에 인가된 전압은 현재의 막을 손상시키지 않을 정도로 충분히 낮다. 그 때, SiO2 또는 SiOF막이 10㎚의 불충분한 두께로 성막된 후에, 예컨대 플라즈마 도입을 위한 무선주파수 전력은 평균 전력 레벨(2차 값)로 조정되고, 스테이지 인가된다. 그래서, 강한 부등방성 플라즈마가 생성되고, 자기바이어스에 대응하는 전위분포가 웨이퍼의 평면방향에 형성된다. 불충분한 SiO2막이 웨이퍼 표면, 예컨대 알루미늄배선상에 형성되기 때문에, 현재의 게이트 산화막에 인가되는 전압은 이 절연막에 의해 보다 낮게 된다. 따라서, 게이트 산화막은 손상을 피할 수 있게 된다.

Description

플라즈마 성막방법 및 그 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예에 따른 플라즈마 프로세스장치를 나타낸 도면도, 제2도는 본 발명의 실시예에 따른 방법의 시퀀스를 나타낸 타임챠트.

Claims (10)

  1. 전자 사이클론 공진을 이용하여 플라즈마가스를 플라즈마로 변환시키고, 처리된 기판상에 절연막을 성막하기 위해 플라즈마로 반응가스를 활성화시키는 플라즈마 성막방법에 있어서, 진공용기에 수용된 스테이지를 향하여 자속을 형성하고, 이 스테이지에서 처리되는 기판을 지지하는 단계와, 진공용기에서 미리 결정된 값의 마이크로파 전력을 인가하고, 플라즈마 가스를 플라즈마로 변환시키기 위해 자계와 협력하여 공진 오퍼레이션을 생성하는 단계 및, 스테이지를 향하여 상기 플라즈마를 도입하기 위해 스테이지상에 바이어스 무선주파수 전력을 인가하고, 바이어스 무선주파수 전력의 레벨이 막 성막의 초기 위상에서의 1차 값과, 막 성막의 초기 위상 후의 1차 값보다 큰 플라즈마 도입을 위한 2차 값으로 조정되는 단계를 구비하여 이루어진 것을 특징으로 하는 플라즈마 성막방법.
  2. 제1항에 있어서, 상기 1차 값이 기판상에 성막된 게이트산화막을 손상으로부터 보호하기 위해 세트되는 것을 특징으로 하는 플라즈마 성막방법.
  3. 제1항에 있어서, 상기 1차 값이 "0"으로 세트되는 것을 특징으로 하는 플라즈마 성막방법.
  4. 제1항에 있어서, 상기 절연막이 SiO2또는 SiOF막을 포함하는 것을 특징으로 하는 플라즈마 성막방법.
  5. 제1항에 있어서, 막 성막의 상기 초기 위상이 바이어스 무선주파수가 상승된 후에 작은 공간에 매립을 확실히 하도록 하는 타이밍을 포함하는 것을 특징으로 하는 플라즈마 성막방법.
  6. 전자 사이클론 공진을 이용하여 플라즈마가스를 플라즈마로 변화시키고, 처리된 기판상에 절연막을 성막하기 이해 플라즈마로 반응가스를 활성화시키는 플라즈마 성막장치에 있어서, 실질적으로 진공에서 처리되고 유지되는 기판을 지지하기 위한 스테이지를 갖춘 진공용기와, 진공용기내의 스테이지를 향하여 자계를 형성하기 위한 자계 형성수단, 진공용기에 미리 결정된 값의 마이크로파 전력을 인가하고, 플라즈마가스를 플라즈마로 변환시키기 위해 자계와 협력하여 공진 오퍼레이션을 생성하기 위한 플라즈마생성 마이크로파 전력 공급수단, 스테이지를 향하여 상기 플라즈마를 도입하기 위해 스테이지상에 바이어스 무선주파수 전력을 인가하기 위한 플라즈마 도입 바이어스 무선주파수 전력 공급수단 및, 막 성막의 초기 위상의 1차 값과, 막 성막의 초기 위상 후의 1차 값보다 큰 플라즈마 도입을 위한 2차 값으로 조정되는 바이어스 무선주파수의 레벨로서 플라즈마 도입 바이어스 무선주파수 전력 공급수단을 제어하기 위한 제어수단을 구비하여 구성된 것을 특징으로 하는 플라즈마 성막장치.
  7. 제6항에 있어서, 상기 1차 값이 기판상에 성막된 게이트 산화막을 손상으로부터 보호하기 위해 세트되는 것을 특징으로 하는 플라즈마 성막장치.
  8. 제6항에 있어서, 상기 1차 값이 "0"으로 세트되는 것을 특징으로 하는 플라즈마 성막장치.
  9. 제6항에 있어서, 상기 절연막이 SiO2또는 SiOF막을 포함하는 것을 특징으로 하는 플라즈마 성막장치.
  10. 제6항에 있어서, 막 성막의 상기 초기 위상이 바이어스 무선주파수 전력이 상승된 후에 작은 공간에 매립을 확실히 하기 위한 타이밍을 포함하는 것을 특징으로 하는 플라즈마 성막방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019960010132A 1995-04-05 1996-04-04 플라즈마 성막방법 KR100415214B1 (ko)

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JP95-106989 1995-04-05
JP10698995 1995-04-05
JP7353549A JPH08335573A (ja) 1995-04-05 1995-12-29 プラズマ成膜方法及びその装置
JP95-353549 1995-12-29

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100356470B1 (ko) * 1999-12-29 2002-10-18 주식회사 하이닉스반도체 반도체 소자의 고밀도 플라즈마막 형성 방법

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* Cited by examiner, † Cited by third party
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US6042901A (en) * 1996-02-20 2000-03-28 Lam Research Corporation Method for depositing fluorine doped silicon dioxide films
JPH1180975A (ja) 1997-09-04 1999-03-26 Speedfam Co Ltd プラズマエッチング装置の耐食システム及びその方法
US7012438B1 (en) 2002-07-10 2006-03-14 Kla-Tencor Technologies Corp. Methods and systems for determining a property of an insulating film
US7064565B1 (en) * 2002-10-31 2006-06-20 Kla-Tencor Technologies Corp. Methods and systems for determining an electrical property of an insulating film
US7248062B1 (en) 2002-11-04 2007-07-24 Kla-Tencor Technologies Corp. Contactless charge measurement of product wafers and control of corona generation and deposition
JP4416569B2 (ja) * 2004-05-24 2010-02-17 キヤノン株式会社 堆積膜形成方法および堆積膜形成装置
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US20070109003A1 (en) * 2005-08-19 2007-05-17 Kla-Tencor Technologies Corp. Test Pads, Methods and Systems for Measuring Properties of a Wafer
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US9481943B2 (en) 2006-11-22 2016-11-01 Soitec Gallium trichloride injection scheme
EP2094406B1 (en) * 2006-11-22 2015-10-14 Soitec Method, apparatus and gate valve assembly for forming monocrystalline group iii-v semiconductor material
US9481944B2 (en) 2006-11-22 2016-11-01 Soitec Gas injectors including a funnel- or wedge-shaped channel for chemical vapor deposition (CVD) systems and CVD systems with the same
US9580836B2 (en) 2006-11-22 2017-02-28 Soitec Equipment for high volume manufacture of group III-V semiconductor materials
WO2008064077A2 (en) 2006-11-22 2008-05-29 S.O.I.Tec Silicon On Insulator Technologies Methods for high volume manufacture of group iii-v semiconductor materials
WO2008064080A1 (en) * 2006-11-22 2008-05-29 S.O.I.Tec Silicon On Insulator Technologies High volume delivery system for gallium trichloride
US8197597B2 (en) 2006-11-22 2012-06-12 Soitec Gallium trichloride injection scheme
KR100870567B1 (ko) * 2007-06-27 2008-11-27 삼성전자주식회사 플라즈마를 이용한 이온 도핑 방법 및 플라즈마 이온 도핑장치
JP2011119779A (ja) * 2011-03-22 2011-06-16 Seiko Epson Corp 強誘電体キャパシタの形成方法、強誘電体キャパシタおよび電子デバイス

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0824114B2 (ja) * 1984-11-09 1996-03-06 株式会社日立製作所 プラズマエッチング方法
JPH0697660B2 (ja) * 1985-03-23 1994-11-30 日本電信電話株式会社 薄膜形成方法
GB2212974B (en) * 1987-11-25 1992-02-12 Fuji Electric Co Ltd Plasma processing apparatus
DE69017744T2 (de) * 1989-04-27 1995-09-14 Fujitsu Ltd Gerät und Verfahren zur Bearbeitung einer Halbleitervorrichtung unter Verwendung eines durch Mikrowellen erzeugten Plasmas.
JP2803304B2 (ja) * 1990-03-29 1998-09-24 富士電機株式会社 絶縁膜を備えた半導体装置の製造方法
JP2598336B2 (ja) * 1990-09-21 1997-04-09 株式会社日立製作所 プラズマ処理装置
US5427827A (en) * 1991-03-29 1995-06-27 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Deposition of diamond-like films by ECR microwave plasma
US5314603A (en) * 1991-07-24 1994-05-24 Tokyo Electron Yamanashi Limited Plasma processing apparatus capable of detecting and regulating actual RF power at electrode within chamber
US5286518A (en) * 1992-04-30 1994-02-15 Vlsi Technology, Inc. Integrated-circuit processing with progressive intermetal-dielectric deposition
US5289010A (en) * 1992-12-08 1994-02-22 Wisconsin Alumni Research Foundation Ion purification for plasma ion implantation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100356470B1 (ko) * 1999-12-29 2002-10-18 주식회사 하이닉스반도체 반도체 소자의 고밀도 플라즈마막 형성 방법

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