KR960035881A - 에스오아이 웨이퍼의 제조방법 - Google Patents

에스오아이 웨이퍼의 제조방법 Download PDF

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Publication number
KR960035881A
KR960035881A KR1019950007597A KR19950007597A KR960035881A KR 960035881 A KR960035881 A KR 960035881A KR 1019950007597 A KR1019950007597 A KR 1019950007597A KR 19950007597 A KR19950007597 A KR 19950007597A KR 960035881 A KR960035881 A KR 960035881A
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South Korea
Prior art keywords
soi substrate
soi
grinding
wafer
polishing
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KR1019950007597A
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English (en)
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KR100327326B1 (ko
Inventor
이경욱
차기호
이병훈
강지중
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김광호
삼성전자 주식회사
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Priority to KR1019950007597A priority Critical patent/KR100327326B1/ko
Publication of KR960035881A publication Critical patent/KR960035881A/ko
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Publication of KR100327326B1 publication Critical patent/KR100327326B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)

Abstract

직접 결합된(direct bonded) SOI (Silicon on Insulator) 웨이퍼의 제작시 야기되는 워퍼치(Warpage)현상을 개선할 수 있는 SOI 웨이퍼의 제조방법이 개시되어 있다.
본 발명은 절연막이 패터닝된 SOI 기판과 핸들링 웨이퍼를 직접 접착시키는 DWB(Direct Wafer Bonding) 공정, 상기 SOI 기판의 엣지를 소정각도록 갈아내는 1차 그라인딩(Grinding) 공정, 상기 SOI 기판의 배면을 소정두께로 갈아내는 2차 그라인딩 고정, 상기 그라인딩 공정후 생성되는 손상층의 두께에 상응하는 SOI 기판의 표면을 식각하는 공정. 및 상기 SOI기판에 패터닝된 절연막을 연마방지막으로 이용하여 상기 SOI 기판을 연마하는 기계화학적 폴리싱(CMP) 공정으로 이루어진다.
본 발명에 의하면, 직접 결합된(direct bonded) SOI 웨이퍼의 제작에 있어서 품위 및 수율을 결정짖는 중요한 인자인 '워피지' (Warpage)를 개선함으로써 고품질의 SOI 소자를 얻을 수 있다.

Description

에스오아이 웨이퍼의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 1E도는 본 발명에 의한 SOI 웨이퍼의 제조방법을 각 단계별로 도시한 공정단면도이다.
제2도는 절연막 패턴을 형성하지 않은 상태의 SOI 기판을 시료로 사용하여, 그라인딩 전/후 및 식각공정 후에 각각 측정한 워피지(Warpage)변화량을 요약한 그래프이다. 제3도는 절연막 패턴을 형성한 상태에서의 SOI 기판을 시료료 사용하여 위피지의 변화량을 측정한 결과를 요약한 그래프이다.

Claims (3)

  1. 절연막의 패터닝된 SOI 기판과 핸들링 웨이퍼를 직접 접착시키는 DWB(Direct Wafer Bonding) 공정; 상기 SOI 기판의 엣지를 소정각도록 갈아내는 1차 그라인딩(Grinding) 공정; 상기 SOI기판의 배면을 소정두께로 갈아내는 2차 그라인딩 공정; 상기 그라인딩 공정후 생성되는 손상층의 두께에 상응하는 SOI기판의 표면을 식각하는 공정; 및 상기 SOI기판에 패터닝된 절연막을 연마방지막으로 이용하여 상기 SOI기판을 연마하는 기계화학적 폴리싱(CMP)공정으로 이루어지는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
  2. 제1항에 있어서, 상기 식각공정은 실리콘 에칭용액을 사용한 습식식각 공정으로 수행되는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
  3. 제2항에 있어서, 상기 실리콘 에칭용액으로 폴리 에쳔트(Poly Etchant)및 KOH 용액중의 어느 하나를 사용하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950007597A 1995-03-31 1995-03-31 에스오아이웨이퍼의제조방법 KR100327326B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007597A KR100327326B1 (ko) 1995-03-31 1995-03-31 에스오아이웨이퍼의제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007597A KR100327326B1 (ko) 1995-03-31 1995-03-31 에스오아이웨이퍼의제조방법

Publications (2)

Publication Number Publication Date
KR960035881A true KR960035881A (ko) 1996-10-28
KR100327326B1 KR100327326B1 (ko) 2002-06-26

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100817718B1 (ko) 2006-12-27 2008-03-27 동부일렉트로닉스 주식회사 반도체 소자 제조방법
KR102061695B1 (ko) 2012-10-17 2020-01-02 삼성전자주식회사 웨이퍼 가공 방법

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