KR960012454A - 몰드에서 수지 압력에 의한 단락 회로를 갖지 않는 반도체 장치 - Google Patents

몰드에서 수지 압력에 의한 단락 회로를 갖지 않는 반도체 장치 Download PDF

Info

Publication number
KR960012454A
KR960012454A KR1019950031141A KR19950031141A KR960012454A KR 960012454 A KR960012454 A KR 960012454A KR 1019950031141 A KR1019950031141 A KR 1019950031141A KR 19950031141 A KR19950031141 A KR 19950031141A KR 960012454 A KR960012454 A KR 960012454A
Authority
KR
South Korea
Prior art keywords
leads
metal wire
semiconductor device
conductive metal
electrical passage
Prior art date
Application number
KR1019950031141A
Other languages
English (en)
Other versions
KR100190213B1 (ko
Inventor
토무 이무라
Original Assignee
가네꼬 히사시
닛폰 덴키 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 닛폰 덴키 가부시끼가이샤 filed Critical 가네꼬 히사시
Publication of KR960012454A publication Critical patent/KR960012454A/ko
Application granted granted Critical
Publication of KR100190213B1 publication Critical patent/KR100190213B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49524Additional leads the additional leads being a tape carrier or flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73229Wire and TAB connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

아일랜드(22b)에 장착된 반도체 칩(21)은 절연 서스펜더 테입(22g)에 의해 지지되는 테입 자동 본딩 리드(22f)를 통해 내부 리드(22d)에 접속되며, 지지 링(22h)이 상기 아일랜드(22b)에 접속된 서스펜션 핀(22c)과 절연 서스펜더 테입(22g)사아에서 접속되어 몰딩 단계 동안 반도체 칩(21)과 테입 자동 본딩 리드(22f) 사이의 원래의 상대적인 위치를 지탱한다.

Description

몰드에서 수지 압력에 의한 단락 회로를 갖지 않는 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명에 따른 리드 프레임으로 조립된 반도체 칩을 보여주는 평면도.
제7도는 제6도의 선 C-C를 따라 절단되어 본 발명에 따른 반도체 장치의 내부 구조를 보여주는 횡단면도.
제8도는 제6도의 선 D-D를 따라 절단되어 다른 각도로부터 반도체 장치의 내부 구조를 보여주는 횡단면도.

Claims (9)

  1. 다수의 접촉 전극(21a;34;59)을 포함하는 반도체 칩(21;32;42;52;62)과; 상기반도체 칩을 장착하기 위한 아일랜드 영역(22b)을 가지는 아일랜드 서브 구조(22a;22b/22c)를 포함하는 리드 프레임 구조(22;31;41;51;61)와; 상기 아일랜드 영역 둘레에 배열된 다수의 첫번째 리드(22d; 22d/33; 22d/43; 22d/33/56; 22d/43/56)와; 상기 다수의 접촉 전극에 각각 접속된 개개의 내측 단부 영역 및 상기 다수의 첫번째 리드에 각각 접속된 개개의 외측 단부 영역을 가지는 다수의 두번째 리드(22f)와; 상기 다수의 두번째 리드 사이에서 상대적인 관계를 유지하기 위해 상기 첫번째 리드와 상기 아일랜드 영역 사이에 제공되며 또한 상기 두번째 리드의 중간 영역에 접속되는 절연 서스펜더(22g)및 상기 반도체 칩 및 상기 리드 프레임 구조를 밀봉하기 위해 몰드된 패키지(23)를 포함하는 반도체 장치에 있어서, 지지 부재(22h)가 상기 절연 서스펜더와 상기 아일랜드 서브 구조 사이에서 상대적인 관계를 유지하기 위해 이들 사이에 접속되는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 아이랜드 서브 구조(22a; 22b/22c)는 상기 아일랜드 영역(22b)에 접속된 단단한 영역(22ca)및 상기 단단한 영역에 접속된 변형가능한 영역(22cb)을 가지며, 상기 지지부재는 상기 절연 서스펜더(22g)와 상기 단단한 영역(22ca)사이에 접속되어 있는 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 다수의 첫번째 리드(22d)및 상기 아일랜드 서브 구조(22a; 22b/22c)는 조합하여 리드 프레임을 형성하며, 상기 다수의 두번째 리드(22f)는 기계적 강도에 있어서 상기 다수의 첫번째 리드보다 더 작은 테입 자동 본딩 리드인 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 또한 상기 리드 프레임 구조(31;41;51;61)는 전압에 할당된 상기 다수의 첫번째 리드중 적어도 하나와 도전 물질로 이루어진 상기 지지 부재(22h)사이에 접속된 첫번째 전기 통로 수단(35a;43)및 상기 반도체 칩에 상기 전압을 공급하기 위한 상기 다수의 접촉 전극 중 적어도 하나와 상기 지지 부재 사이에 접속된 두번째 전기 통로 수단(35b;44)을 부가로 포함하는 것을 특징으로 하는 반도체 장치.
  5. 제4항에 있어서, 상기 첫번째 전기 통로 및 상기 두번째 전기 통로는 첫번째 도전 금속 와이어(35a)와 두번째 금속 와이어(35b)에 의해 제공되는 것을 특징으로 하는 반도체 장치.
  6. 제4항에 있어서, 상기 첫번째 전기 통로와 상기 두번째 전기 통로는 상기 다수의 첫번째 리드의 적어도 하나와 도전 금속 와이어(44)의 연장부에 의해 제공되는 것을 특징으로 하는 반도체 장치.
  7. 제4항에 있어서, 상기 지지 부재(22h)는 상기 절연 서스펜더(22g)의 상측 및 하측 표면의 하나에 접속되며, 또한 상기 리드 프레임 구조(51;61)는 상기 절연 서스펜더(22g)의 상기 상측 및 하측 표면의 다른 것을 덮는 절연 레이어(53)를 포함하며, 도전판 부재(55)는 상기 절연 레이어(53)를 통해 상기 절연 서스펜더(22g)에 의해 지지되며, 세번째 전기 통로 수단(57)은 다른 전압에 할당된 상기 다수의 첫번째 리드 중 적어도 다른 하나(56)와 상기 도전판 부재 사이에 접속되어 있으며, 네번째 전기 통로 수단(58)은 상기 도전판 부재와 상기 다수의 접촉 전극의 적어도 다른 하나(59)사이에 접속되어 있는 것을 특징으로 하는 반도체 장치.
  8. 제7항에 있어서, 상기 첫번째 전기 통로, 두번째 전기 통로, 세번째 전기 통로 및 네번째 전기 통로는 첫번째 도전 금속 와이어(35a), 두번째 도전 금속 와이어(35b), 세번째 도전 금속 와이어(57)및 네번째 도전 금속 와이어(58)에 의해 제공되는 것을 특징으로 하는 반도체 장치.
  9. 제7항에 있어서, 상기 첫번째 전기 통로, 두번째 전기 통로, 세번째 전기 통로 및 네번째 전기 통로는 상기 다수의 첫번째 리드의 적어도 하나(43)와 첫번째 도전 금속 와이어(44), 두번째 도전 금속 와이어(57)및 세번째 도전 금속 와이어(58)의 연장부에 의해 제공되는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950031141A 1994-09-22 1995-09-21 몰드에서 수지 압력에 의한 단락 회로를 갖지 않는 반도체 장치 KR100190213B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP22781494A JP2542795B2 (ja) 1994-09-22 1994-09-22 樹脂封止型半導体装置
JP94-227814 1994-09-22

Publications (2)

Publication Number Publication Date
KR960012454A true KR960012454A (ko) 1996-04-20
KR100190213B1 KR100190213B1 (ko) 1999-06-01

Family

ID=16866802

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950031141A KR100190213B1 (ko) 1994-09-22 1995-09-21 몰드에서 수지 압력에 의한 단락 회로를 갖지 않는 반도체 장치

Country Status (3)

Country Link
US (1) US5731962A (ko)
JP (1) JP2542795B2 (ko)
KR (1) KR100190213B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367826B1 (ko) * 1997-09-11 2003-08-19 제일모직주식회사 불포화 폴리에스테르계 난연성 벌크 몰딩 컴파운드의 제조방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956282B1 (en) * 1997-11-05 2005-10-18 Texas Instruments Incorporated Stabilizer/spacer for semiconductor device
US6949824B1 (en) * 2000-04-12 2005-09-27 Micron Technology, Inc. Internal package heat dissipator
KR102414593B1 (ko) 2015-12-30 2022-06-30 엘지디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281738A (ja) * 1985-10-07 1987-04-15 Hitachi Micro Comput Eng Ltd リ−ドフレ−ムおよびそれを用いた半導体装置
JPH0834282B2 (ja) * 1988-10-31 1996-03-29 日本電気株式会社 半導体装置用リードフレーム
JPH02125652A (ja) * 1988-11-04 1990-05-14 Nec Corp リードフレーム
JPH02146740A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体装置
JPH0425144A (ja) * 1990-05-21 1992-01-28 Shinko Electric Ind Co Ltd 3層tab用テープを用いた半導体装置及び3層tab用テープの製造方法
KR100552353B1 (ko) * 1992-03-27 2006-06-20 가부시키가이샤 히타치초엘에스아이시스템즈 리이드프레임및그것을사용한반도체집적회로장치와그제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367826B1 (ko) * 1997-09-11 2003-08-19 제일모직주식회사 불포화 폴리에스테르계 난연성 벌크 몰딩 컴파운드의 제조방법

Also Published As

Publication number Publication date
US5731962A (en) 1998-03-24
JP2542795B2 (ja) 1996-10-09
JPH0897243A (ja) 1996-04-12
KR100190213B1 (ko) 1999-06-01

Similar Documents

Publication Publication Date Title
US4984059A (en) Semiconductor device and a method for fabricating the same
JP3646023B2 (ja) 大面積の接続ポストと改良された外形を有する高電流容量半導体装置パッケージとリードフレーム
US6734551B2 (en) Semiconductor device
KR960005972A (ko) 수지 밀폐형 반도체 장치 및 그 제조 방법
JP2528991B2 (ja) 樹脂封止型半導体装置及びリ―ドフレ―ム
KR960706194A (ko) 계층화된 도전 평면을 갖는 리드 프레임(a lead frame having layered conductive planes)
KR0144164B1 (ko) 엘오씨 반도체 패키지 및 반도체 장치를 패키징하는 방법
KR920001689A (ko) 반도체장치 및 그 제조방법
US20030197255A1 (en) Semiconductor device
KR970067736A (ko) 리이드 프레임과 그것을 사용한 반도체장치 및 그 제조방법
KR950021435A (ko) 수지 봉지형 반도체 장치 및 그 제조 방법
KR900005587A (ko) 반도체 디바이스 및 그 제작방법
KR920010853A (ko) 수지봉지형 반도체장치
KR970060468A (ko) 반도체 소자 및 그 제조 방법
KR900017153A (ko) 반도체 장치 및 그 제조방법
JP3026426B2 (ja) 樹脂封止型半導体装置とその製造方法及びその金型構造
KR960012454A (ko) 몰드에서 수지 압력에 의한 단락 회로를 갖지 않는 반도체 장치
KR970067782A (ko) 유기 응력 이완층에 의해 균열없이 플라스틱 패키지내에 성형된 반도체 장치
JP3010924B2 (ja) 半導体装置
JP2917928B2 (ja) 半導体装置の製造方法
KR940008060A (ko) 반도체 집적회로 장치
KR19980078349A (ko) 반도체 패키지 및 그 제조방법
JPS6120758Y2 (ko)
KR100525091B1 (ko) 반도체 패키지
KR100268925B1 (ko) 리드프레임및이를이용한반도체패키지

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030109

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee