KR960001989A - 데이타 프로세서 - Google Patents
데이타 프로세서 Download PDFInfo
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- KR960001989A KR960001989A KR1019950014677A KR19950014677A KR960001989A KR 960001989 A KR960001989 A KR 960001989A KR 1019950014677 A KR1019950014677 A KR 1019950014677A KR 19950014677 A KR19950014677 A KR 19950014677A KR 960001989 A KR960001989 A KR 960001989A
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- South Korea
- Prior art keywords
- load
- unit
- instructions
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- load instruction
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- 239000000872 buffer Substances 0.000 claims abstract 10
- 230000008707 rearrangement Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
공개된 데이타 프로세서(10)는 다중 적재/기억 및 적재/기억 스트링 명령을 간단한 적재 또는 기억 명령의 순차로서 적재/기억 유닛(28)으로 디스패치한다. 순차기유닛(18)은 적재/기억 유닛이 각각의 단순한 적재 명령의 데이타를 다시 기록하도록 개명 버퍼(34)의 입력을 할당한다. 이 전략은 연속 명령들로 진행하는 초기 데이타를 능률화 시킨다. 반대로 순차기 유닛은 그것이 간단한 기억 명령의 오피랜드를 공급할 수 있으면 개명버퍼 태그를 적재/기억 유닛으로 공급한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 구성된 데이타 프로세서의 블럭도,
제4도는 제3도에 묘사된 기억 행렬(store queue)의 각 입력이 있을 수 있는 가능한 상태들을 예시하는 상태전이도.
Claims (5)
- 실행 유닛을 가지며 적재 명령을 수행하기 위한 데이타 프로세서에 있어서, 다수의 아키텍쳐 레지스터와, 상기 다수의 아키텍쳐 레지스터에 결합되고 다수의 입력을 구비하며 상기 다수의 입력들의 각각은 다수의 명령의 상이한 명령의 다수의 결과들의 상이한 결과를 버퍼하는 개명버퍼와, 상기 개명 버퍼에 결합되고 디스패치된 각 적재 명령-태그쌍에 대해서 메모리 시스템으로부터의 어드레스에 의해 색인된 데이타를 요구하며 상기 데이타를 태그에 의해 색인된 개명 버퍼의 상기 다수의 입력중 한 입력에 버퍼하고, 상기 적재명령-태그쌍은 상기 개명 버퍼의 상기 다수의 입력중 한 입력을 식별하는 태그를 구비하는 적재 유닛 및, 상기 개명 버퍼에 결합되고 N*W 바이트를 요구하는 다중 적재 명령을 수신하고 N적재 명령 태그쌍들을 상기 적재 유닛으로 디스패치하며, 여기서 N과W는 정수이고 N은 1보다 크며 상기 다수의 아키텍쳐 레지스터의 각각은 크기가 W 바이트인 순차기 유닛을 구비하는 것을 특징으로 하는 데이타 프로세서.
- 제1항에 있어서, 상기 순차기 유닛은 한 어드레스를 상기 적재 유닛으로 디스패치하고 상기 적재 유닛은 N 적재 명령-태그쌍들중(N-1)적재 명령-태그쌍의 (N-1)어드레스들을 발생하는 어드레스 계산 수단을 더 구비하는 것을 특징으로 하는 데이타 프로세서.
- 제2항에 있어서, 상기 어드레스 계산 수단은, 제1멀티플렉서의 출력과 제2멀티플렉서의 출력을 합산하기 위한 덧셈기와, 상기 N적재 명령-태그쌍들의 각각의 제1필드 또는 번호 W를 교대로 출력하기 위한 상기 제1멀티플렉서와, 상기 N 적재 명령-태그쌍들의 각각의 제2필드 또는 상기 덧셈기의 출력을 교대로 출력하기 위한 상기 제2멀티플렉서 및, 상기 제1및 제2멀티플렉서의 입력들을 선택하기 위한 제어 회로를 구비하는 것을 특징으로 하는 데이타 프로세서.
- 제3항에 있어서, 상기 순차기 유닛은 디스패치된 명령들의 순차를 기억하기 위한 재배열 버피를 더 구비하고, 상기 순차기 유닛은 상기 개명 버퍼의 상기 다수의 입력중 한 입력을 상기 순차에 응답하여 상기 다수의 아키텍쳐 레지스터들중 한 레지스터로 복사하는 것을 특징으로 하는 데이타 프로세서.
- 제4항에 있어서, 상기 적재 유닛으로 디스패치된 각 적재 명령에 대해서 상기 적재 유닛은 상기 어드레스에 의해 색인된 데이타를 상기 메모리 시스템에 기억시키고, 상기 순차기 유닛은 M*W 바이트를 기억하는 다중기억 명령을 수시하며, 여기서 M은 1보다 큰 정수이고, 상기 순차기 유닛은 M 기억 명령들을 상기 적재 유닛으로 디스패치시키는 것을 특징으로 하는 데이타 프로세서.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US25527194A | 1994-06-03 | 1994-06-03 | |
US255,271 | 1994-06-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960001989A true KR960001989A (ko) | 1996-01-26 |
Family
ID=22967591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950014677A KR960001989A (ko) | 1994-06-03 | 1995-06-03 | 데이타 프로세서 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5664215A (ko) |
EP (1) | EP0686912B1 (ko) |
JP (1) | JPH09120360A (ko) |
KR (1) | KR960001989A (ko) |
CN (1) | CN1144934A (ko) |
DE (1) | DE69506623T2 (ko) |
Families Citing this family (67)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5898854A (en) * | 1994-01-04 | 1999-04-27 | Intel Corporation | Apparatus for indicating an oldest non-retired load operation in an array |
US5974240A (en) * | 1995-06-07 | 1999-10-26 | International Business Machines Corporation | Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution |
US5694565A (en) * | 1995-09-11 | 1997-12-02 | International Business Machines Corporation | Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions |
US5926642A (en) * | 1995-10-06 | 1999-07-20 | Advanced Micro Devices, Inc. | RISC86 instruction set |
US5822602A (en) * | 1996-07-23 | 1998-10-13 | S3 Incorporated | Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity |
US5859999A (en) * | 1996-10-03 | 1999-01-12 | Idea Corporation | System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers |
US7272703B2 (en) * | 1997-08-01 | 2007-09-18 | Micron Technology, Inc. | Program controlled embedded-DRAM-DSP architecture and methods |
JPH11212788A (ja) * | 1998-01-28 | 1999-08-06 | Toshiba Corp | プロセッサのデータ供給装置 |
US6192461B1 (en) * | 1998-01-30 | 2001-02-20 | International Business Machines Corporation | Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle |
US6035394A (en) * | 1998-02-17 | 2000-03-07 | International Business Machines Corporation | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel |
FR2777370B1 (fr) * | 1998-04-09 | 2000-06-23 | Sgs Thomson Microelectronics | Architecture de dsp optimisee pour les acces memoire |
US6094716A (en) * | 1998-07-14 | 2000-07-25 | Advanced Micro Devices, Inc. | Register renaming in which moves are accomplished by swapping rename tags |
US6308260B1 (en) * | 1998-09-17 | 2001-10-23 | International Business Machines Corporation | Mechanism for self-initiated instruction issuing and method therefor |
US6301654B1 (en) * | 1998-12-16 | 2001-10-09 | International Business Machines Corporation | System and method for permitting out-of-order execution of load and store instructions |
US6349382B1 (en) * | 1999-03-05 | 2002-02-19 | International Business Machines Corporation | System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order |
EP1050797A1 (en) * | 1999-05-03 | 2000-11-08 | STMicroelectronics S.A. | Execution of instructions in a computer program |
US6629233B1 (en) * | 2000-02-17 | 2003-09-30 | International Business Machines Corporation | Secondary reorder buffer microprocessor |
US6791564B1 (en) | 2000-05-05 | 2004-09-14 | Ipfirst, Llc | Mechanism for clipping RGB value during integer transfer |
US6868491B1 (en) | 2000-06-22 | 2005-03-15 | International Business Machines Corporation | Processor and method of executing load instructions out-of-order having reduced hazard penalty |
US6725358B1 (en) * | 2000-06-22 | 2004-04-20 | International Business Machines Corporation | Processor and method having a load reorder queue that supports reservations |
GB0023697D0 (en) * | 2000-09-27 | 2000-11-08 | Univ Bristol | Register assignment in a processor |
US20100223295A1 (en) * | 2000-12-06 | 2010-09-02 | Io Informatics, Inc. | Applied Semantic Knowledgebases and Applications Thereof |
US20020156756A1 (en) * | 2000-12-06 | 2002-10-24 | Biosentients, Inc. | Intelligent molecular object data structure and method for application in heterogeneous data environments with high data density and dynamic application needs |
JP3497832B2 (ja) * | 2001-03-28 | 2004-02-16 | 株式会社半導体理工学研究センター | ロード・ストアキュー |
US7266811B2 (en) * | 2001-09-05 | 2007-09-04 | Conexant Systems, Inc. | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor |
US7315934B2 (en) * | 2002-03-06 | 2008-01-01 | Matsushita Electric Industrial Co., Ltd. | Data processor and program for processing a data matrix |
US20050015542A1 (en) * | 2003-07-15 | 2005-01-20 | Gateway, Inc. | Multiple write storage device |
US8144156B1 (en) * | 2003-12-31 | 2012-03-27 | Zii Labs Inc. Ltd. | Sequencer with async SIMD array |
US8745627B2 (en) * | 2005-06-27 | 2014-06-03 | Qualcomm Incorporated | System and method of controlling power in a multi-threaded processor |
US7434032B1 (en) * | 2005-12-13 | 2008-10-07 | Nvidia Corporation | Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators |
JP5019022B2 (ja) * | 2006-03-20 | 2012-09-05 | 日本電気株式会社 | データロード方法及びデータ処理装置 |
GB2442499B (en) * | 2006-10-03 | 2011-02-16 | Advanced Risc Mach Ltd | Register renaming in a data processing system |
US9135005B2 (en) * | 2010-01-28 | 2015-09-15 | International Business Machines Corporation | History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties |
CN102141905B (zh) * | 2010-01-29 | 2015-02-25 | 上海芯豪微电子有限公司 | 一种处理器体系结构 |
US8938605B2 (en) * | 2010-03-05 | 2015-01-20 | International Business Machines Corporation | Instruction cracking based on machine state |
US8645669B2 (en) | 2010-05-05 | 2014-02-04 | International Business Machines Corporation | Cracking destructively overlapping operands in variable length instructions |
US9378019B2 (en) | 2011-04-07 | 2016-06-28 | Via Technologies, Inc. | Conditional load instructions in an out-of-order execution microprocessor |
US9043580B2 (en) | 2011-04-07 | 2015-05-26 | Via Technologies, Inc. | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) |
US9176733B2 (en) | 2011-04-07 | 2015-11-03 | Via Technologies, Inc. | Load multiple and store multiple instructions in a microprocessor that emulates banked registers |
US9244686B2 (en) | 2011-04-07 | 2016-01-26 | Via Technologies, Inc. | Microprocessor that translates conditional load/store instructions into variable number of microinstructions |
US9317288B2 (en) | 2011-04-07 | 2016-04-19 | Via Technologies, Inc. | Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US8880857B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
US8880851B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US9128701B2 (en) | 2011-04-07 | 2015-09-08 | Via Technologies, Inc. | Generating constant for microinstructions from modified immediate field during instruction translation |
US9274795B2 (en) | 2011-04-07 | 2016-03-01 | Via Technologies, Inc. | Conditional non-branch instruction prediction |
US9146742B2 (en) | 2011-04-07 | 2015-09-29 | Via Technologies, Inc. | Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA |
US9032189B2 (en) | 2011-04-07 | 2015-05-12 | Via Technologies, Inc. | Efficient conditional ALU instruction in read-port limited register file microprocessor |
US8924695B2 (en) | 2011-04-07 | 2014-12-30 | Via Technologies, Inc. | Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor |
US9292470B2 (en) | 2011-04-07 | 2016-03-22 | Via Technologies, Inc. | Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program |
US9645822B2 (en) | 2011-04-07 | 2017-05-09 | Via Technologies, Inc | Conditional store instructions in an out-of-order execution microprocessor |
US9336180B2 (en) | 2011-04-07 | 2016-05-10 | Via Technologies, Inc. | Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode |
US9141389B2 (en) | 2011-04-07 | 2015-09-22 | Via Technologies, Inc. | Heterogeneous ISA microprocessor with shared hardware ISA registers |
EP2631786B1 (en) * | 2011-04-07 | 2018-06-06 | VIA Technologies, Inc. | Load multiple and store multiple instructions in a microprocessor that emulates banked registers |
US9898291B2 (en) | 2011-04-07 | 2018-02-20 | Via Technologies, Inc. | Microprocessor with arm and X86 instruction length decoders |
US8914616B2 (en) | 2011-12-02 | 2014-12-16 | Arm Limited | Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed |
US9201656B2 (en) * | 2011-12-02 | 2015-12-01 | Arm Limited | Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers |
US20140310500A1 (en) * | 2013-04-11 | 2014-10-16 | Advanced Micro Devices, Inc. | Page cross misalign buffer |
JP6344022B2 (ja) * | 2014-04-08 | 2018-06-20 | 富士通株式会社 | 演算処理装置および演算処理装置の制御方法 |
US11281481B2 (en) | 2014-07-25 | 2022-03-22 | Intel Corporation | Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture |
CN105117202B (zh) * | 2015-09-25 | 2018-11-27 | 上海兆芯集成电路有限公司 | 具有融合保留站结构的微处理器 |
US10037211B2 (en) | 2016-03-22 | 2018-07-31 | International Business Machines Corporation | Operation of a multi-slice processor with an expanded merge fetching queue |
US10346174B2 (en) * | 2016-03-24 | 2019-07-09 | International Business Machines Corporation | Operation of a multi-slice processor with dynamic canceling of partial loads |
US10761854B2 (en) | 2016-04-19 | 2020-09-01 | International Business Machines Corporation | Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor |
US10037229B2 (en) | 2016-05-11 | 2018-07-31 | International Business Machines Corporation | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions |
US10318419B2 (en) | 2016-08-08 | 2019-06-11 | International Business Machines Corporation | Flush avoidance in a load store unit |
US11113056B2 (en) * | 2019-11-27 | 2021-09-07 | Advanced Micro Devices, Inc. | Techniques for performing store-to-load forwarding |
US11687347B2 (en) * | 2021-05-25 | 2023-06-27 | Andes Technology Corporation | Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4287561A (en) * | 1978-03-16 | 1981-09-01 | International Business Machines Corporation | Address formulation interlock mechanism |
JPH02190930A (ja) * | 1988-12-29 | 1990-07-26 | Internatl Business Mach Corp <Ibm> | ソフトウエア命令実行装置 |
EP0495162A3 (en) * | 1991-01-16 | 1994-05-18 | Ibm | Storage management |
US5416911A (en) * | 1993-02-02 | 1995-05-16 | International Business Machines Corporation | Performance enhancement for load multiple register instruction |
-
1995
- 1995-05-29 DE DE69506623T patent/DE69506623T2/de not_active Expired - Fee Related
- 1995-05-29 EP EP95108173A patent/EP0686912B1/en not_active Expired - Lifetime
- 1995-06-02 CN CN95106550A patent/CN1144934A/zh active Pending
- 1995-06-03 KR KR1019950014677A patent/KR960001989A/ko not_active Application Discontinuation
- 1995-06-05 JP JP7160147A patent/JPH09120360A/ja active Pending
-
1996
- 1996-03-27 US US08/622,159 patent/US5664215A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0686912A3 (en) | 1997-03-12 |
DE69506623D1 (de) | 1999-01-28 |
US5664215A (en) | 1997-09-02 |
JPH09120360A (ja) | 1997-05-06 |
DE69506623T2 (de) | 1999-07-22 |
CN1144934A (zh) | 1997-03-12 |
EP0686912B1 (en) | 1998-12-16 |
EP0686912A2 (en) | 1995-12-13 |
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