DE69506623T2 - Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb - Google Patents

Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb

Info

Publication number
DE69506623T2
DE69506623T2 DE69506623T DE69506623T DE69506623T2 DE 69506623 T2 DE69506623 T2 DE 69506623T2 DE 69506623 T DE69506623 T DE 69506623T DE 69506623 T DE69506623 T DE 69506623T DE 69506623 T2 DE69506623 T2 DE 69506623T2
Authority
DE
Germany
Prior art keywords
execution unit
data processor
load commands
executing load
executing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69506623T
Other languages
English (en)
Other versions
DE69506623D1 (de
Inventor
Seungyoon Peter Song
David P Burgess
Mark A Kearney
Marvin A Denman
Lavanya Kling
Milton M Hood
Graham R Murphy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69506623D1 publication Critical patent/DE69506623D1/de
Application granted granted Critical
Publication of DE69506623T2 publication Critical patent/DE69506623T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69506623T 1994-06-03 1995-05-29 Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb Expired - Fee Related DE69506623T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25527194A 1994-06-03 1994-06-03

Publications (2)

Publication Number Publication Date
DE69506623D1 DE69506623D1 (de) 1999-01-28
DE69506623T2 true DE69506623T2 (de) 1999-07-22

Family

ID=22967591

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69506623T Expired - Fee Related DE69506623T2 (de) 1994-06-03 1995-05-29 Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb

Country Status (6)

Country Link
US (1) US5664215A (de)
EP (1) EP0686912B1 (de)
JP (1) JPH09120360A (de)
KR (1) KR960001989A (de)
CN (1) CN1144934A (de)
DE (1) DE69506623T2 (de)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898854A (en) * 1994-01-04 1999-04-27 Intel Corporation Apparatus for indicating an oldest non-retired load operation in an array
US5974240A (en) * 1995-06-07 1999-10-26 International Business Machines Corporation Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution
US5694565A (en) * 1995-09-11 1997-12-02 International Business Machines Corporation Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5822602A (en) * 1996-07-23 1998-10-13 S3 Incorporated Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity
US5859999A (en) * 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
JPH11212788A (ja) * 1998-01-28 1999-08-06 Toshiba Corp プロセッサのデータ供給装置
US6192461B1 (en) * 1998-01-30 2001-02-20 International Business Machines Corporation Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle
US6035394A (en) * 1998-02-17 2000-03-07 International Business Machines Corporation System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel
FR2777370B1 (fr) * 1998-04-09 2000-06-23 Sgs Thomson Microelectronics Architecture de dsp optimisee pour les acces memoire
US6094716A (en) * 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
US6308260B1 (en) * 1998-09-17 2001-10-23 International Business Machines Corporation Mechanism for self-initiated instruction issuing and method therefor
US6301654B1 (en) * 1998-12-16 2001-10-09 International Business Machines Corporation System and method for permitting out-of-order execution of load and store instructions
US6349382B1 (en) * 1999-03-05 2002-02-19 International Business Machines Corporation System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order
EP1050797A1 (de) * 1999-05-03 2000-11-08 STMicroelectronics S.A. Befehlausführung in einem Rechnersystem
US6629233B1 (en) * 2000-02-17 2003-09-30 International Business Machines Corporation Secondary reorder buffer microprocessor
US6791564B1 (en) 2000-05-05 2004-09-14 Ipfirst, Llc Mechanism for clipping RGB value during integer transfer
US6725358B1 (en) * 2000-06-22 2004-04-20 International Business Machines Corporation Processor and method having a load reorder queue that supports reservations
US6868491B1 (en) 2000-06-22 2005-03-15 International Business Machines Corporation Processor and method of executing load instructions out-of-order having reduced hazard penalty
GB0023697D0 (en) * 2000-09-27 2000-11-08 Univ Bristol Register assignment in a processor
US20020156756A1 (en) * 2000-12-06 2002-10-24 Biosentients, Inc. Intelligent molecular object data structure and method for application in heterogeneous data environments with high data density and dynamic application needs
US20100223295A1 (en) * 2000-12-06 2010-09-02 Io Informatics, Inc. Applied Semantic Knowledgebases and Applications Thereof
JP3497832B2 (ja) * 2001-03-28 2004-02-16 株式会社半導体理工学研究センター ロード・ストアキュー
US7266811B2 (en) * 2001-09-05 2007-09-04 Conexant Systems, Inc. Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor
US7315934B2 (en) * 2002-03-06 2008-01-01 Matsushita Electric Industrial Co., Ltd. Data processor and program for processing a data matrix
US20050015542A1 (en) * 2003-07-15 2005-01-20 Gateway, Inc. Multiple write storage device
US8144156B1 (en) * 2003-12-31 2012-03-27 Zii Labs Inc. Ltd. Sequencer with async SIMD array
US8745627B2 (en) * 2005-06-27 2014-06-03 Qualcomm Incorporated System and method of controlling power in a multi-threaded processor
US7434032B1 (en) * 2005-12-13 2008-10-07 Nvidia Corporation Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators
JP5019022B2 (ja) * 2006-03-20 2012-09-05 日本電気株式会社 データロード方法及びデータ処理装置
GB2442499B (en) * 2006-10-03 2011-02-16 Advanced Risc Mach Ltd Register renaming in a data processing system
US9135005B2 (en) * 2010-01-28 2015-09-15 International Business Machines Corporation History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties
CN102141905B (zh) * 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
US8938605B2 (en) * 2010-03-05 2015-01-20 International Business Machines Corporation Instruction cracking based on machine state
US8645669B2 (en) 2010-05-05 2014-02-04 International Business Machines Corporation Cracking destructively overlapping operands in variable length instructions
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
EP2508982B1 (de) * 2011-04-07 2016-03-30 VIA Technologies, Inc. Steuerregister-Mapping in einem heterogenen-Befehlsatzarchitektur Prozessor
US8924695B2 (en) 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US8880857B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US9201656B2 (en) 2011-12-02 2015-12-01 Arm Limited Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers
US8914616B2 (en) 2011-12-02 2014-12-16 Arm Limited Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed
US20140310500A1 (en) * 2013-04-11 2014-10-16 Advanced Micro Devices, Inc. Page cross misalign buffer
JP6344022B2 (ja) * 2014-04-08 2018-06-20 富士通株式会社 演算処理装置および演算処理装置の制御方法
US11281481B2 (en) 2014-07-25 2022-03-22 Intel Corporation Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture
CN106557301B (zh) * 2015-09-25 2019-05-07 上海兆芯集成电路有限公司 经由多级保留站结构的发射指令分派方法
US10037211B2 (en) 2016-03-22 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor with an expanded merge fetching queue
US10346174B2 (en) * 2016-03-24 2019-07-09 International Business Machines Corporation Operation of a multi-slice processor with dynamic canceling of partial loads
US10761854B2 (en) 2016-04-19 2020-09-01 International Business Machines Corporation Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor
US10037229B2 (en) 2016-05-11 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
US10318419B2 (en) 2016-08-08 2019-06-11 International Business Machines Corporation Flush avoidance in a load store unit
US11113056B2 (en) * 2019-11-27 2021-09-07 Advanced Micro Devices, Inc. Techniques for performing store-to-load forwarding
US11687347B2 (en) * 2021-05-25 2023-06-27 Andes Technology Corporation Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4287561A (en) * 1978-03-16 1981-09-01 International Business Machines Corporation Address formulation interlock mechanism
JPH02190930A (ja) * 1988-12-29 1990-07-26 Internatl Business Mach Corp <Ibm> ソフトウエア命令実行装置
EP0495162A3 (en) * 1991-01-16 1994-05-18 Ibm Storage management
US5416911A (en) * 1993-02-02 1995-05-16 International Business Machines Corporation Performance enhancement for load multiple register instruction

Also Published As

Publication number Publication date
US5664215A (en) 1997-09-02
DE69506623D1 (de) 1999-01-28
EP0686912A3 (de) 1997-03-12
EP0686912B1 (de) 1998-12-16
EP0686912A2 (de) 1995-12-13
KR960001989A (ko) 1996-01-26
CN1144934A (zh) 1997-03-12
JPH09120360A (ja) 1997-05-06

Similar Documents

Publication Publication Date Title
DE69506623T2 (de) Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb
DE69430943D1 (de) Verfahren und System zum Überwachen von Datei-Attributen
DE69423158T2 (de) Verfahren und Vorrichtung zur Konfiguration von Rechnerprogrammen mit Hilfe verfügbarer Unterprogramme
DE69032635T2 (de) Verfahren und Vorrichtung zur Erkennung von Betriebsmittelkonflikten in einer Pipeline-Verarbeitungseinheit
DE69434717D1 (de) Datenverarbeitungsgerät das als Host arbeitet und Verfahren um das Datenverarbeitungsgerät zu steuern
DE69724516D1 (de) Rechnersystem und Verfahren zur Ausführung von architekturspezifischem Programmcode mit geringen Laufzeitspeicherbereichsanforderungen
DE69534558D1 (de) Effizientes Verfahren, Gerät und Rechnerprogramm zur Auswertung graphischer Programmiersprache
DE69527674D1 (de) Zentralprozessoreinheit mit integrierten Grafikfunktionen und Verfahren zur Durchführung von Grafikbefehle in dieser Zentralprozessoreinheit
DE69841089D1 (de) System und Verfahren zum Gebrauch einer einzigen Steuerungsschaltung für eine Vielzahl von Bildverarbeitungskomponenten
DE69721634D1 (de) Computersystem und Verfahren für die Ausführung von mehreren Threads mit reduziertem Runtime-Speicherbedarf
DE69325086D1 (de) Verfahren und System für spekulative Befehlsausführung
DE69617511T2 (de) Verfahren und Gerät zum Verwalten von Objekten in einer verteilten Objektbetriebsumgebung
DE59406787D1 (de) Radargerät und verfahren zu seinem betrieb
DE59410364D1 (de) Verfahren zur prüfung von elektronischen steuergeräten
DE69535191D1 (de) Verfahren und vorrichtung zur reduktion durch rauschen erzeugter datenfehler unter verwendung von störaustastung
DE69323196T2 (de) Rechnersystem und Verfahren zur Ausführung von mehreren Aufgaben
DE69710515T2 (de) Verfahren und Vorrichtung zur Bestimmung von Wartezuständen auf einer Zyklusbasis in einem Datenverarbeitungssystem
DE69227741D1 (de) System und Verfahren zur Aufrüstung von Computer-Hardware und Software
DE1042887T1 (de) Verfahren und vorrichtung zur durchführung von support an einer auswahlgruppe für eine koppelpunktsteuereinheit
DE69524811D1 (de) Gerät und Verfahren zur Fernausführung von Rechnerprozessen
DE69720100D1 (de) Verfahren und Gerät zur Löschung von Objekten in einer Multifaden-Umgebung
DE69830387D1 (de) Elektronisches Gerät mit Verfahren und Vorrichtung zur Ausführung von Befehlsbündeln
DE69731696D1 (de) Verfahren und Vorrichtung zur Datenausgangssteuerung und Steuerungsprogramm dafür
DE69616671D1 (de) Verfahren und Anordnung zur Ausführung von Rechnerbefehlen
DE69528428T2 (de) Gerät und Verfahren zur Verjüngung von Software

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee