KR950024278A - 반도체소자 제조방법 - Google Patents

반도체소자 제조방법 Download PDF

Info

Publication number
KR950024278A
KR950024278A KR1019940001476A KR19940001476A KR950024278A KR 950024278 A KR950024278 A KR 950024278A KR 1019940001476 A KR1019940001476 A KR 1019940001476A KR 19940001476 A KR19940001476 A KR 19940001476A KR 950024278 A KR950024278 A KR 950024278A
Authority
KR
South Korea
Prior art keywords
forming
semiconductor device
oxide film
formation
manufacturing
Prior art date
Application number
KR1019940001476A
Other languages
English (en)
Other versions
KR970002428B1 (ko
Inventor
박해수
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940001476A priority Critical patent/KR970002428B1/ko
Publication of KR950024278A publication Critical patent/KR950024278A/ko
Application granted granted Critical
Publication of KR970002428B1 publication Critical patent/KR970002428B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체소자 제조방법에 관한 것으로, 종래 반도체소자는 단차가 발생하여 접촉상 형성시의 습,건식식각을 수행할 경우 단차에 의한 추가식각이 요구되며, 이에따라 다음공정에서 금속선의 스텝커버리지 불량형성 및 디바이스 특성에 나쁜영항을 주는 문제점이 있었다.
본 발명은 이러한 문제점을 해결하기 위하여 습식식각율의 차이를 이용하여 단차를줄이는 동시에 추가식각부분을 제거하여 소자손상방지 및 후속 금속박막의 스텝커버리지을 향상시킬 수 있도록 하는 반고체소자 제조방법을 제공하는 것이다.

Description

반도체소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 반도체소자 단면구조도.
제4도의 (가)내지(마)는 본 발명 반도체소자의 제조공정도.

Claims (3)

  1. 실리콘기판상에 필드산화막을 형성하는 공정과, 상기 필드산화막 위에 제1다결정실리콘을 형성하는 공정과, 고온산화막패턴을 형성하는 공정화, 제2다결정실리콘을 형성하는 공정과, BPSG막을 형성하는 공정과, 단차가 높은 부분에 불순물이온을 주입하는 공정과, 접촉창을 정의하는 공정과, 상기 접촉창을 식각한후 금속막을 형성하는 공정으로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.
  2. 제1항에 있어서, 불순물주입공정은 습식식각율이 빠른 불순물이온을 주입하는 것을 특징으로 하는 반도체소자 제조방법.
  3. 제2항에 있어서, 습식식각율이 빠른 불순물이온으로 인(P+)을 사용하는 것을 특징으로 하는 반도체소자 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940001476A 1994-01-27 1994-01-27 반도체소자 제조방법 KR970002428B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940001476A KR970002428B1 (ko) 1994-01-27 1994-01-27 반도체소자 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940001476A KR970002428B1 (ko) 1994-01-27 1994-01-27 반도체소자 제조방법

Publications (2)

Publication Number Publication Date
KR950024278A true KR950024278A (ko) 1995-08-21
KR970002428B1 KR970002428B1 (ko) 1997-03-05

Family

ID=19376340

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940001476A KR970002428B1 (ko) 1994-01-27 1994-01-27 반도체소자 제조방법

Country Status (1)

Country Link
KR (1) KR970002428B1 (ko)

Also Published As

Publication number Publication date
KR970002428B1 (ko) 1997-03-05

Similar Documents

Publication Publication Date Title
US4182023A (en) Process for minimum overlap silicon gate devices
US4956314A (en) Differential etching of silicon nitride
US6399448B1 (en) Method for forming dual gate oxide
US5637529A (en) Method for forming element isolation insulating film of semiconductor device
US5521411A (en) Transistor spacer etch pinpoint structure
KR100526460B1 (ko) 리세스 채널 구조를 갖는 반도체 소자 및 그 제조 방법
KR950024278A (ko) 반도체소자 제조방법
KR100244402B1 (ko) 반도체소자의 트렌치 아이솔레이션 제조방법
KR100272264B1 (ko) 반도체 소자의 제조방법
KR100282425B1 (ko) 캐패시터의제조방법
KR100325443B1 (ko) 모스트랜지스터제조방법
KR100234728B1 (ko) 모스 전계효과 트랜지스터 제조방법
KR100189727B1 (ko) 반도체 소자의 액티브 영역 확대 및 소자 격리방법
KR940011802B1 (ko) 디램 셀의 제조방법
KR950027954A (ko) 반도체 소자의 콘택홀 형성방법
KR960002071B1 (ko) 반도체 소자의 콘택 형성방법
KR930008842B1 (ko) 자기정렬 매몰 콘택트를 이용한 디램 셀의 제조방법
KR910002810B1 (ko) 이온 주입에 의한 저온산화막 경사 에칭 방법
KR100215857B1 (ko) 트랜지스터의 제조방법
KR0178995B1 (ko) 반도체 메모리소자의 커패시터 제조방법
KR940001351A (ko) 반도체 소자의 격리방법
KR100215871B1 (ko) 반도체 소자의 제조방법
KR930003269B1 (ko) 반도체소자의 측벽 형성방법
KR930008647B1 (ko) 고집적 소자의 셀로우 정크션 형성방법
KR950000104B1 (ko) 반도체 소자 격리 방법 및 셀 구조

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050221

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee