KR940027241A - 반도체 레이져 소자 및 그 제조방법 - Google Patents
반도체 레이져 소자 및 그 제조방법 Download PDFInfo
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- KR940027241A KR940027241A KR1019930009357A KR930009357A KR940027241A KR 940027241 A KR940027241 A KR 940027241A KR 1019930009357 A KR1019930009357 A KR 1019930009357A KR 930009357 A KR930009357 A KR 930009357A KR 940027241 A KR940027241 A KR 940027241A
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
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Abstract
본 발명은 반도체 레이저 소자에 관한 것이다.
본 발명 반도체 레이저 소자는 그 몸체 중간에 소정 높이의 리지가 마련된 메사구조의 크래딩 레이어와, 상기 상부 크래딩 레이어의 상부에 형성되는 것으로 상기 리지의 상단면에 대응되는 부분이 결여된 절연층과, 상기 절연층의 상부에 형성되며, 상기 절연층의 결여부를 통해 상기 상부 크래딩 레이어와 전기적으로 접속되는 상부 전극을 구비하며, 상기 리지의 양측면에는 소정 두께의 이온 주입에 의한 전류 제한층이 마련되어 있다. 따라서 리지의 폭을 자유롭게 변경할 수 있고, 또한 반복적 재현성이 높은 장점이 나타난다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 3 내지 제 6 도는 본 발명 제조방법에 의한 단계적 반도체 레이저 소자의 제조 순서도.
Claims (3)
- 기판과 레이저가 발진하는 활성영역층과, 상기 활성영역층과 기판의 사이에 마련되는 하부 크래딩 레이어, 상기 활성영역층의 상부에 마련되며, 그 몸체 중간에 소정 높이의 리지가 마련된 메사구조의 상부 크래딩 레이어와, 상기 상부 크래딩 레이어의 상부에 형성되는 것으로 상기 리지의 상단면에 대응되는 부분이 결여된 절연층과, 상기 절연층의 상부에 형성되며, 상기 절연층의 결여부를 통해 상기 상부 크래딩레이어와 전기적으로 접속되는 상부 전극, 상기 상부 전극에 대응되는 것으로 상기 기판의 저면에 형성되는 하부 전극을 구비하는 반도체 레이저 소자에 있어서, 상기 리지의 양측면에 소정 두께의 이온 공급에 의한 전류 제한층이 마련되어 상기 상부 전극으로부터의 전류 이동 경로가 상기 리지의 폭에 비해 좁게 마련된 것을 특징으로 하는 반도체 레이저 소자.
- 제 1 항에 있어서, 상기 리지는 상기 상부 크래딩레이어, ㉿핑 레이어, 그리고 p+-GaAs의 적층을 갖는 것을 특징으로 하는 반도체 레이저 소자.
- 기판에 하나 혹은 다수의 활성영역층과 상기 활성영역층의 상하에 마련되는 상하부 크래딩 레이어를 순차적으로 형성하는 단계, 상기 크래딩 레이어의 위에 적어도 하나의 콘택트층을 형성하는 단계 상기 콘택트층의 표면으로부터 상기 상부 크래딩 레이어의 표면 소정깊이에까지 소정패턴으로 전류제한 영역을 형성하는 단계, 상기 상부 크래딩 레이어의 전류제한 영역을 소정 패턴으로 에칭하여 그 양측면에 소정 두께의 전류제한층이 마련된 소정높이의 리지를 형성하는 단계, 상기 리지의 상단면에 대응하는 부위를 제외한 상기 상부 크래딩 레이어와 상기 전류제한층의 위에 소정 두께로 절연층을 형성하는 단계, 상기 절연층의 상부에 전극을 형성하여 상기 상부 크래딩 레이어의 상기 전극과 전기적으로 접속되게 하는 단계를 포함하는 것을 특징으로 하는 반도체 레이저 소자의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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KR1019930009357A KR100255689B1 (ko) | 1993-05-27 | 1993-05-27 | 반도체 레이져 소자 및 그 제조방법 |
US08/528,862 US5612251A (en) | 1993-05-27 | 1995-09-15 | Manufacturing method and device for a polycrystalline silicon |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019930009357A KR100255689B1 (ko) | 1993-05-27 | 1993-05-27 | 반도체 레이져 소자 및 그 제조방법 |
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KR940027241A true KR940027241A (ko) | 1994-12-10 |
KR100255689B1 KR100255689B1 (ko) | 2000-05-01 |
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KR1019930009357A KR100255689B1 (ko) | 1993-05-27 | 1993-05-27 | 반도체 레이져 소자 및 그 제조방법 |
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US4436557A (en) * | 1982-02-19 | 1984-03-13 | The United States Of America As Represented By The United States Department Of Energy | Modified laser-annealing process for improving the quality of electrical P-N junctions and devices |
CA1239706A (en) * | 1984-11-26 | 1988-07-26 | Hisao Hayashi | Method of forming a thin semiconductor film |
JPH0810668B2 (ja) * | 1985-10-31 | 1996-01-31 | 旭硝子株式会社 | 多結晶シリコン膜の製造方法 |
US4851363A (en) * | 1986-07-11 | 1989-07-25 | General Motors Corporation | Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses |
JPH0828509B2 (ja) * | 1986-11-07 | 1996-03-21 | 株式会社リコー | 薄膜トランジスターの活性領域の形成方法 |
JPS6425515A (en) * | 1987-07-22 | 1989-01-27 | Hitachi Ltd | Manufacture of semiconductor device |
GB2215126B (en) * | 1988-02-19 | 1990-11-14 | Gen Electric Co Plc | Process for manufacturing a thin film transistor |
JPH0233935A (ja) * | 1988-07-23 | 1990-02-05 | Seiko Epson Corp | 薄膜トランジスタの製造方法 |
JP2624318B2 (ja) * | 1988-11-25 | 1997-06-25 | 三菱電機株式会社 | イメージセンサおよびその製造方法 |
-
1993
- 1993-05-27 KR KR1019930009357A patent/KR100255689B1/ko not_active IP Right Cessation
-
1995
- 1995-09-15 US US08/528,862 patent/US5612251A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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KR100255689B1 (ko) | 2000-05-01 |
US5612251A (en) | 1997-03-18 |
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